We developed and applied a new circuit, called the "Self-controllable Voltage Level (SVL)" circuit, not only to expand both "write" and "read" stabilities, but also to achieve a low stand-by power and data holding capability in a single low power supply, 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher the wordline voltages for a "read" and "write" operation, respectively. It can also adaptively lower and higher the memory cell supply voltages for the "write" and "hold" operations, and "read" operation, respectively. A Si area overhead of the SVL circuit is only 1.383% of the conventional SRAM.

We developed and applied a new circuit, called the self-controllable voltage level (SVL) circuit, to achieve not only low standby power dissipation (Pst) while retaining data, but also to switch significantly quickly between an operational mode and a standby mode, in a single power source, 90-nm CMOS delay flip-flop (D-FF). The Pst of the developed D-FF is only 5.585 nW/bit, 14.81% of the 37.71 nW/bit of the conventional D-FF at a supply voltage (Vdd) of 1.0 V. The static-noise margin of the developed D-FF is 0.2576 V, and that of the conventional D-FF is 0.3576 V (at Vdd of 1.0 V). The Si area overhead of the SVL circuit is 11.62% of the conventional D-FF.

The SVL circuit not only improve “read” and “write” characteristics of SRAMs, but also reduce the stand-by powers of the SRAMs. Therefore, SRAMs incorporating SVL circuits are very useful for use in low supply voltage, battery-driven portable systems.

A DVFS controlled 90-nm CMOS multimedia processor was developed. To make full use of the advantages of DVFS, we developed the A2BC algorithm that can predict the optimum clock frequency and the optimum supply voltage. The measured power dissipation of the DVFS controlled multimedia processor was significantly reduced. Thus, DVFS employing the A2BC algorithm is one of the most useful power reduction for future video encoding applications.

To significantly reduce the number of block-matching (BM) processes for motion vector estimation (ME), we have developed a fast sub-sampling block matching (FSBM) algorithm for H.264. FSBM consists of three steps: a pre-processing step to define conditions for the second step, an alternate sub-sampling process to quickly find the precise location at which the third step starts, and cyclic four-point searches to pinpoint the final motion vector. FSBM not only improves the processing speed of a full search (FS) algorithm by a factor of up to 866, but also that of the simplified unsymmetrical-cross multi-hexagon-grid search (S-UMHS) algorithm for HDTV by a factor of up to 2.18, while achieving the same visual quality as that of FS.

A low leakage power, 180-nm 1K-b SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a “Self-controllable Voltage Level (SVL)” circuit was only 3.7nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDDof 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVTS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage (Vd) and the optimum clock frequency (fc.) before each block matching process stalls. Power dissipation of the MK processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to 29.1 muW, which was only 3% that of a conventional ME processor.

The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were fabricated using 0.18-mum CMOS technology. The first and second stages of the driver consisted of a single inverter and m inverters, respectively, and the register array stage was constructed with N delay flip-flops (D-FFs). A single inverter in the second stage drove N/m D-FFs where N was fixed at 40 and m varied from 1 to 40. Minimum PTand tdTwere 251 muW and 0.640 ns, respectively and were both obtained at an m of 8. These values were 48.6% and 29.4% of maximum PTand tdTrespectively. Simulated and measured results agreed well with these SPICE simulated results.

To drastically reduce the dynamic power (P/sub AT/) and the leakage power (P/sub ST/), while to keep speed of a CMOS square-root (SR) circuit, a new algorithm, new architectures and a new leakage reduction circuit were developed. Using these techniques, a 90-nm CMOS LSI was fabricated. The P/sub AT/ and P/sub ST/ of the new SR circuit were reduced to about 1/4 and 1/33 those of a conventional SR circuit. Measured results agreed well with simulated results.

A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel*128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system.>

Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of image processing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.

A real-time video signal processor (VSP), suitable for VLSI implementation, is proposed. In order to obtain software controllability for video signal processing in a real-time environment, the VSP employs a multiprocessor configuration, where a plural number of video signal processing modules (VSPMs) are connected to input, output and feedback buses. Each VSPM processes its own assigned sub-images without communicating from/to other VSPMs. As the VSP needs no overhead for VSPM communication, the number of VSPMs involved does not affect the VSP system performance. The homogeneous processor based approach, employed in VSP, will become the most suitable LSI implementation methodology in the near future, due to processor module regularity and system flexibility.

Development of compact, high-speed, and low power adaptive transversal filters (ATF's) has been of great interest. Such ATF's have already been successfully fabricated in monolithic form employing a short channel MOSFET process and switched capacitor technique, using only complete analog circuit technology while eliminating inherent analog problems. This IC with five taps works with both ±5 V and 10 V supplies at a clock rate of more than 250 kHz. It has been designed for multipurpose applications such as a decision feedback equalizer (DFE), echo canceller (EC), and linear equalizer (LE), the last of which has already been reported [5]. The architecture to realize these applications will be described first. Much discussion is presented on the investigation of the operation, characteristics, and performance limitations of this IC in the DFE mode, from which those in the EC mode for two-wire full-duplex data transmission can be understood. For a single echo with magnitude of one half that of the original signal and delay time of one clock period from the original signal, and convergence factor of 0.2 for weight adaptation, the DFE operating at the clock rate of 100 kHz completes equalization within about 1.2 ms resulting in a residual rms distortion of -45.4 dB. The dominant performance limitation factors are found to be both the correlator harmonic distortion and transversal filter noise, but not the convolver harmonic distortion which is the dominant factor for the LE.