Runtime noise management systems typically rely on on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the system alarm rate subject to a given system failure rate constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 20.6% reduction in system alarm rate under the same system failure rate constraint. We further show that with the help of Iddqmeasurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. It further reduces the alarm rate by 12.3% on average compared with uniform threshold approach. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for systematic studies of on-chip noise sensor utilization.

The lack of accurate yet open to public simulation infrastructure has puzzled researchers in the memcomputing area for sometime. In this paper, we propose for the first time a full tool chain called MSim that supports the cycle-accurate microarchitecture level simulation for memcomputing studies. With MSim, the performance gains of utilizing memcomputing for arbitrary applications on user configurable computer system architectures can be evaluated in high accuracy. In addition, MSim provides flexible interfaces with pervasive object-oriented design, which makes it well-suited as a good base platform for researchers to explore new memcomputing technologies.

Runtime noise management systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and the runtime performance loss (RPL) due to false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the system failure rate subject to a given RPL constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 32.1% reduction in system failure rate under the same RPL constraint. We further show that with the help of Iddqmeasurements during testing which reveals process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage. Such an approach further reduces the system failure rate by 25.0% on average compared with the uniform threshold approach, under the same RPL constraint. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for systematic studies of on-chip noise sensor utilization.

Runtime noise management systems can enforce power integrity without significantly increasing design margins. These systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. Unfortunately, it remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection, or how to best set the threshold voltage for these sensors. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric to be maximized. We then put forward an efficient algorithm to solve it, which is proven to attain the best result in the class of polynomial complexity approximations. We further solve the problem to minimize the system failure rate subject to a given runtime performance loss (RPL) constraint. Experimental results on a set of industrial power grid designs show that, compared to a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aimed at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x, and 6.2x, respectively. The trade-off between the system failure rate and the RPL is also presented. To the best of the authors' knowledge, this is the very first in-depth work on noise sensor deployment.

On-chip temperature and stress sensors are important for runtime system management techniques tackling thermomechanical reliability issues in 3-D integrated circuits (ICs). However, traditional temperature and stress sensor designs require large calibration overhead to improve accuracy, which incurs significant cost for massive production. To address the challenge, in this paper, we propose a novel temperature-stress cosensor design for 3-D ICs. By exploring the inherent reciprocity of temperature and stress mechanisms, it achieves runtime self-calibration such that no dedicated calibration effort is needed. Simulation results show that the cosensor achieves 0.26°C and 0.43 MPa accuracy on average in temperature and stress measurements, respectively, when evaluated in [60 °C}, 140 ° C]. In addition, the accuracy of self-calibrated sensors remains within 1.1 °C and 2.3 MPa when there exists up to 5% measurement noise, which shows that the self-calibration process is relatively insensitive to various noises.

3D physical design needs accurate device model of through-silicon vias (TSVs). In this paper, physics-based electrical-thermal model is introduced for both signal and dummy thermal TSVs with the consideration of nonlinear electrical-thermal dependence. Taking thermal-reliable 3D clock-tree synthesis as a case-study to verify the effectiveness of the proposed TSV model, one nonlinear programming-based clock-skew reduction problem is formulated to allocate thermal TSVs for clock-skew reduction under non-uniform temperature distribution. With a number of 3D clock-tree benchmarks, experiments show that under the nonlinear electrical-thermal TSV model, insertion of thermal TSVs can effectively reduce temperature-gradient introduced clock-skew by 58.4% on average, and has 11.6% higher clock-skew reduction than the result under linear electrical-thermal model.

A 3D reconfigurable power switch network is introduced to optimally provide demand-supply matching between on-chip multi-output power converters and many-core microprocessors. For effective DVFS power management of many cores by area-efficient on-chip power converters, the reconfigurable power switch network supports space and time multiplexed access between power converters and cores. An integer linear programming is deployed to find one configuration of space-time multiplexing that can match between supply and demand with balanced utilization. The overall power management system is verified in SystemC-AMS based models. Experiment results show that the proposed design achieves 35.36% power saving on average when compared to the one without using the proposed power management.

The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the issue, recently several works have shed light on the possibilities of dynamic noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume, either implicitly or explicitly, that the placement of the sensors is given. It remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric (SQM) to be maximized. We then put forward an efficient algorithm to solve it, which is proved to be optimal in the class of polynomial complexity approximations. Experimental results on a set of industrial power grid designs show that compared with a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aiming at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x and 6.2x, respectively.

The CTE mismatch-induced stress in 3D ICs may initiate cracks from the interface between a TSV and its dielectric liner, and propagates them on the silicon substrate surface. If a crack grows beyond the keep-out-zone (KOZ) of a TSV, it will jeopardize the reliability of the devices along its propagation path. While such threat can be eliminated by a sufficiently large KOZ, significant area overhead will be incurred. Given the low probability of crack occurrence, we argue that a much more economical approach is to keep KOZ small and filter out bad chips with cracks growing beyond the KOZ during testing. However, traditional microscope or X-ray diffraction based crack detection techniques are cost-prohibitive for massive productions. To address this issue, this paper proposes a novel crack sensor design with very little design or testing overhead. It is simply formed by doping the area surrounding a suspicious TSV. By measuring its DC resistances during testing, cracks that grow beyond the doped area can be easily detected. In addition, through empirical studies on crack dynamics in various TSV configurations, we provide deployment guidelines to minimize the number of sensors needed. To the best of our knowledge, this is the first work to propose a macroscale crack detection technique.

Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in academia to model, design or optimize the power delivery networks (PDNs) in 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none is available in the context of 3D. As a consequence, most existing literature resorts to ad-hoc designs by artificially stacking 2D PDNs for experiments, rendering the results less convincing. In this paper, we put forward a set of ten PDN benchmarks that are extracted from industrial 3D designs. These designs are carefully selected such that they cover a wide range of functionality, size, TSV number, tier number and packaging style. We hope that the released benchmarks can facilitate and promote research in 3D PDNs.

Real-time and decentralized energy resource allocation has become the main feature to develop for the next generation energy management system (EMS). In this paper, a minority game (MG)-based EMS (MG-EMS) is proposed for smart buildings with hybrid energy sources: main energy resource from electrical power-grid and renewable energy resource from solar photovoltaic (PV) cells. Compared to the traditional static and centralized EMS (SC-EMS), and the recent multi-agent-based EMS (MA-EMS) based on price-demand competition, our proposed MG-EMS can achieve up to 51× and 147× utilization rate improvements respectively regarding to the fairness of solar energy resource allocation. In addition, the proposed MG-EMS can also reduce peak energy demand for main power-grid by 30.6%. As such, one can significantly reduce the cost and improve the stability of micro-grid of smart buildings with a high utilization rate of solar energy.

As one of the newly introduced resistive random access memory (ReRAM) devices, this paper has shown an in-depth study of conductive-bridging random access memory (CBRAM) for non-volatile memory (NVM) computing. Firstly, a CBRAM-crossbar based memory is evaluated with accurate physical-level model and circuit-level characterization. It is then deployed as NVM component with a 3D hybrid integration of SRAM/DRAM, where one layer of CBRAM-crossbar is designed for data-retention under power gating to reduce leakage power from SRAM/DRAM at other layers. Moreover, a block-level data-retention scheme is designed to only write back dirty data from SRAM/DRAM to CBRAM-crossbar. When compared to the hybrid memory using phase-change random access memory (PCRAM) as data-retention, our CBRAM-based hybrid memory achieves 16x faster migration time and 4x less migration power for hibernating transition. When compared to the FeRAM-based bit-wise data-retention, our approach also achieves 17x smaller area and 8x smaller power under the same data migration speed.

The reliability of SRAM-based Field Programmable Gate Array (FPGA) is susceptible to Single Event Upset (SEU) fault. To investigate the fault impact, particular the fault in interconnects on FPGA functionality, this paper proposes a SEU fault analysis framework by evaluating the fault with a unified metric. This metric, termed as criticality, quantifies the sensitivity of FPGA functional failure to the SEU fault on logical and interconnect configuration bits. Considering the post layout information, our framework can characterize the SEU fault with respect to different FPGA architectures and CAD algorithms, such that the sensitivity of FPGA functional failure can be investigated in detail during design phase. The experiment result quantitatively shows that the configuration bits in interconnects dominate those in LUTs, several times both in bit number and criticality contribution. The ratio of their criticalities is even higher when LUT input size increases from 4 to 6. The higher criticality of interconnects than their LUT counterpart is due to their natural sensitivity to functional failure instead of their majority of bits. In addition, it is also shown that, among the three common types of switch boxes, the Subset switch box is less fault tolerant than Wilton and Universal.

Boolean matching is one of the most important fundamental algorithms in FPGA synthesis and architecture evaluations. However, existing Boolean matchers for FPGAs, even with numerous improvements, are still not scalable to complex PLBs and large circuits. This paper aims to improve the efficiency of Boolean matching using lookup tables implemented by Bloom filters, which can store terabyte-lookup tables with a desktop PC. The key improvement is to efficiently prune a large set of non-implementable functions use the Bloom filter. Using the area-oriented re-synthesis as an application, the experiments on a broad selection of benchmark sets show that the re-synthesis with our improved Boolean matcher is 18X faster than the one with an optimized SAT-based Boolean matcher, while preserving the quality of the re-synthesizer.

Software as a Service (SaaS) 1.0 signifcantly lowers the infrastructure and maintenance cost and increases the accessibility of the software by hosting software via the web. Compared with SaaS 1.0, SaaS 2.0 is more flexible since it leverages software tools from both server and client sides with closer interaction between them. The SaaS 2.0 paradigm provides new opportunities and challenges for EDA. In this paper, we take Boolean matching, one of the core sub algorithms in logic synthesis for field programmable gate arrays (FPGAs), as a case study. We investigate the advantages and challenges of implementing a scalable EDA algorithm under SaaS 2.0 paradigm from a technical perspective. We propose SaaS-BM, a new Boolean matching algorithm customized to take full advantage of the cloud while addressing concerns such as security and the internet bandwidth limit. Extensive experiments are performed under a networked environment with concurrent accesses. Integrated into a post-mapping re-synthesis algorithm minimizing area, the proposed SaaS-BM is 863X times faster than state-of-the-art SAT-based Boolean matching with 0.5% area overhead. Compared with a recent Bloom Filter-based Boolean matching algorithm, our proposed SaaS-BM is 53X times faster on large circuits with no area overhead.