From design, verification, and manufacturing to testing, Artificial Intelligence (AI) is reshaping the technologies applied to Electronic Design Automation (EDA) tools in semiconductor industry. Utilizing AI not only shortens the design cycle through faster and optimized design implementation, analyses, and decisions, but also provides engineers with new insights and guidance for innovation and root cause analysis.

Fueled by advanced packaging technologies, the chiplet-based design approach is moving the design methodology in the semiconductor industry from monolithic System-on-Chip (SoC) to System-in-Package (SiP). In SiP, a complex design is disaggregated into multiple smaller and functionally specialized ICs. These ICs are integrated through 2.5D, where the ICs are packaged side-by-side on a common interpose, and/or 3D, where the dies are stacked on top of each other. The chiplet approach not only shortens the time to market and lowers the design cost but also improves the yield when compared to the monolithic SoC. However, it introduces many unique challenges for the IC test due to interconnected density, heterogenous integration, and thermal management, etc.

As the manufactural technologies are moving to deep sub-micron process, the defects inside the design library cells occur more often during manufacture. Cell-Aware Testing (CAT) had been proposed to improve the test quality on detecting the cell internal defects. In CAT, the analog simulator is used to simulate the cell input combinations exhaustively for every defect to identify all the cell input combinations that detect the defects in the cells. However, it becomes less practical to handle the complex cells with large number of inputs and to consider multiple capture cycles because of the computational complexity of the analog simulation when processing the extremely large number of the input combinations. In this paper, we propose to model the design library cells as the ATPG library cells at the transistor level such that the existing ATPG tools can be used to generate the exhaustive test sets for every cell internal defect more efficiently. The generated test patterns are further divided into the hard-detection set and the soft-detection set. Only the test patterns from the soft-detection set need to be simulated by the analog simulator to verify the capability and the confidence level on detecting the defect. Using the proposed method can dramatically speed up the time-consuming step in the CAT flow, that is, for every defect to identify all input combinations that detect the defect through the analog simulation.

This paper describes a novel methodology of creating scan-based at-speed structural patterns to analyze and validate functional critical paths on latch-based high performance CPU cores. Silicon data comparison with traditional transition fault patterns and functional patterns are conducted and reported to illustrate the effectiveness of the proposed scheme.

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used.

This paper presents the structural testing challenges for Intel's high-performance IA Cores and the novel ATPG solutions developed to overcome them. Intel's IA Cores employ a design structure which, poses unique testing challenges for industry-standard design-for-testing (DFT) tools. First, the prevalent use of both latches and flip-flops while employing a two-phase clocking scheme. Second, the structural-based patterns reuse the functional clock network, hence keeping the performance and power profile similar to that of a functional test. Such design properties introduce unique Automatic-Test-Pattern-Generation (ATPG) challenges. The paper will introduce the innovative enhancements to the Design Rule Checks (DRCs), developed to handle these unique designs.

Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.

Fault diagnosis patterns distinguish pairs of faults and are used to improve fault diagnosis resolution. Earlier, several methods to generate fault diagnosis patterns have been proposed. We demonstrate that all but one earlier proposed methods may generate invalid patterns when the circuit under test (CUT) has X sources, which is typically true for industrial designs. The earlier proposed method that can generate valid diagnosis patterns in the presence of X sources uses two copies of the CUT to generate diagnosis tests, thus requiring larger memory and run time. In addition, to use ATPGs that generate test to detect single fault, earlier methods require circuit modification for each pair of faults to be distinguished, requiring multiple loadings of the CUT, thus increasing run times. We propose a method to generate valid diagnosis patterns using a single copy of the CUT and using a standard single fault detection ATPG with minor modification. The proposed method does not require modifying the circuit to generate diagnosis patterns. Experimental results are presented to demonstrate the effectiveness of the proposed method.

In order to reduce the power consumption and improve the circuit performance, the dual-edge triggered flip-flop (DETFF) has been using as sequential element in the designs. Comparing with conventional single-edge triggered flip-flop (SETFF), applying the scan based structural test for the designs using DETFFs faces additional challenges. In this paper, we address some of the challenges, including a non-intrusive design of the scan DETFF, ATPG models of the scan DETFF, and several test generation issues, in order to achieve highest structural test quality for such kind of designs. The test generation results on modified ISCAS-89 and ITC-99 designs demonstrate the effectiveness of the proposed strategies.

Scan chain diagnosis plays an important role in silicon debug and yield ramp-up since 10% to 30% of chip failures are caused by scan chain failures. Failure data collected on testers is limited by buffer sizes to capture the failing responses from scan chains, especially since scan chain failures produce a large amount of failing responses. In this paper, we propose a new pattern selection method to maximize the chain diagnosis resolution when limited failure information is collected from the tester. Experimental results on industrial designs show our method achieves higher diagnosis resolution than previous method.

Typically IDDQ measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using IDDQ measurements is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed IDDQ based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.

At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

Detecting the defects inside the CMOS cells, especially the stuck-open faults, has gained a lot of attentions in recent years. It had been shown the test set generated by using the transition fault model is not sufficient to detect the stuck-open faults. In this paper, we propose an enhanced transition fault model, named cell transition, to improve the quality of the transition test set on detecting the stuck-open faults inside the CMOS cells. The fault sites targeted by the proposed model are placed at the cell boundary in order to keep the fault population similar to the transition fault model. Experimental results demonstrate the cell transition test set detects more stuck-open faults than the transition test set while the test coverage achieved for the transition faults is close to that obtained by the transition test set. Moreover, the number of generated tests is slightly higher than the transition test set.

In this paper we consider detection of faults in CMOS cells that are more complex than primitive gates. We derive a single set of tests based on functional description of the cells. The tests derived, if applied, detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell, in any implementation of the cell functions. We give results on an industrial design to demonstrate the benefits of the proposed tests relative to standard stuck-at, cell exhaustive and transition fault tests in covering faults in such cells.

This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work seamlessly with existing sequential linear decompressors. Experimental results obtained for industrial designs demonstrate the effectiveness of the proposed method at reducing TDV in high compression configurations.

Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.

Testing for small-delay defects (SDDs) requires fault-effect propagation along the longest testable paths. However, identification of the longest testable paths requires high CPU time, and the sensitization of all such paths leads to large pattern counts. Dynamic test compaction for small-delay defects is therefore necessary to reduce test-data volume. We present a new technique for identifying the longest testable paths through each gate in order to accelerate test generation for SDDs. The resulting test patterns sensitize the longest testable paths that pass through each SDD site. An efficient dynamic test compaction method based on structural analysis is presented to reduce the pattern count substantially, while ensuring that all the longest paths for each SDD are sensitized. Simulation results for a set of ISCAS 89 and IWLS 05 benchmark circuits demonstrate the effectiveness of this method.

Scan based at-speed testing has become mandatory in industry to detect delay defects today in order to maintain test quality and reduce test cost. However, the effects of power supply droop during test application often introduce timing uncertainty, such as clock stretch and additional gate delay. It leads to false failure and test escape during test and makes the application of the at-speed scan testing become a challenge task to screen out delay defects successfully. In this paper, we review existing studies about the power supply droop and the methods to reduce its impact on at-speed scan testing.

Test data compression has become a dominant approach to reduce the test cost today. Majority of test compression schemes are based on the fact that the generated test cubes have very few specified bits. This paper studies additional test cube properties and utilizes them to reduce the test data volume (TDV) further. Two approaches are proposed in this paper. The first one requires no additional hardware and the second one is based on the new DFT hardware, named background chains. The proposed approaches can be combined with other test compression schemes to achieve additional TDV reduction. The experimental results based on embedded deterministic test (EDT) show the proposed approaches achieve significant TDV reduction for industrial designs.

In this paper we examine several embedded low power test schemes that we have proposed over the last few years. These solutions are aimed at reducing the switching activity during all scan-based test operations, particularly including those developed for BIST or deployed to perform on-chip test data compression.

Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction.

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

One of the common failures found in manufactured ICs are interconnect opens. While stuck-at and transition fault automatic test pattern generation (ATPG) patterns can detect open defects, these fault models do not catch all of them. This poster describes a project and research with a new open fault model to supplement the others. The project consists of many parts that target specific types of known open defects.

This paper presents a clock control architecture for designs with multiple clock domains, and a novel mix of existing ATPG techniques as well as novel ATPG enhancements. The combination of the ATPG techniques and the clock control hardware lowers the number of test patterns in a fully automated flow, while maintaining the high coverage that is required nowadays by production test. Experimental results are shown for two industrial designs.

Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also result in extra yield loss. To address these issues, this paper first presents a detailed investigation of a benchmark circuit's switching activity during different modes of operation. Specifically, the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be approximately 2.5 times more than the average number of transitions during the circuit's normal functional operation. A DFT-based approach for reducing circuit switching activity during scan shift is proposed. Instead of inserting additional logic at the gate level that may introduce additional delay on critical paths, the proposed method modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization. Our experiments show that significant power reduction can be achieved with very low overhead.

High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on industrial designs show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences.

This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.

Power consumption during scan-based test becomes a major concern in modern nanometer technologies. Gating the outputs of scan cells can dramatically reduce the scan shift power. In this paper, we utilize the same gating logic at the outputs of scan cells to reduce the capture power consumption. This is achieved by inserting block enable cells (BECs) into the design to dynamically control the gating logic. During capture the BECs enable the gating logic to block the transitions originated from a subset of scan chains or scan segments propagating to combinational logic in order to reduce capture power. The implementation of the proposed method in test compression environment is also discussed. The experimental results on industrial designs show the significant capture power reduction by using proposed techniques.

This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture.

Interconnect opens are one of major failure mechanisms in contemporary deep sub-micro designs. In this paper, we present three test generation methods, static dominant, dynamic dominant, and double observation, to generate the tests for the interconnect opens. The first two methods take the electrical behavior of the interconnect opens into consideration during test generation and the third method is applied when the parasitic capacitances between the open net and its neighboring nets are not dominant parameter to determine the voltage at the open net. The experimental results show that N-detection stuck-at test set and transition test set are not sufficient to achieve high test coverage on detecting interconnect opens, especially when the voltage at the interconnect open is determined by a large number of neighboring nets. The top-up test patterns generated by using proposed test generation methods help to improve the test quality on detecting interconnect open defects.

Power consumption during scan-based test becomes a concern in nanometer technologies. Previous test power reduction techniques that insert additional logic in gate-level circuits may result in timing violations. In this paper, we show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously, we identify power-sensitive scan cells at the prototyping gate level, and we map these cells to their corresponding signal/variable bits at the RT-level. Additional RTL code is added to freeze these power- sensitive bits in order to reduce scan shift power consumption. Experimental results on ITC99 benchmarks show that on average more than 22% power reduction can be achieved when we only freeze the top 1% of power-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level.

In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified. Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions.

Timing-aware ATPG [1] has been shown to be an effective method for generating high-quality test sets that detect small delay defects through the longest paths. However, this method usually results in a much higher test pattern count than the traditional transition fault test generation. In this paper, we propose a new criterion that identifies a subset of transition faults to be targeted by the timing-aware ATPG in order to reduce test pattern count while minimizing the impact on the overall delay test quality. The new criterion utilizes the minimal static slack to classify certain transition faults as timing-critical. The test pattern count reduction is achieved by restricting the timing-aware ATPG to targeting the timing-critical transition faults while using traditional transition fault test generation for the remaining transition faults. The experimental results for the industrial circuits show the effectiveness of the proposed method.

In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs

When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage drops leading to larger gate delays which may cause good chips to fail tests. This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests. Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

In this paper, we investigate the impacts of the untestable defects, modeled by stuck-open faults and bridging faults, on the quality of transition fault test set. The presence of those defects may make some transition faults to be tested invalidly if they are not considered during transition fault test generation. As a result, the chips with delay defects may escape from testing. Two incremental ATPG procedures are proposed to address invalidly tested transition faults. Experimental results show that the quality of the transition fault test set can be maintained with few additional test patterns.

In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them.

A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of the gross gate delay defect and the distributed delay defect are large enough to cause timing violation for all the paths passing through the fault site and the fault propagation path. Experimental results demonstrate that high fault coverage can be achieved in a reasonable amount of time and the test set size is comparable to the test set size generated for the transition fault model.

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of the-art microcontroller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip high-speed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed.

To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize multiple clocks in the design effectively and efficiently in order to dramatically reduce test pattern count without sacrificing fault coverage or causing clock skew problem. This is achieved by pulsing multiple non-interactive clocks simultaneously and applying a clock concatenation technique. Experimental results on several industrial circuits show significant test pattern count reduction by using the proposed test generation procedures.

This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic decision ordering, conflict driven recursive learning and conflict learning. An important feature shared by all these techniques is that they are triggered by the occurrence of a conflict in the generation of tests. Hence, they are not active all the time nor for all the faults. This feature allows the ATPG system that uses these techniques to resolve hard-to-resolve faults with far fewer backtracks and leaves the system as efficient as before in the absence of conflicts. We have incorporated these techniques into a commercial D-algorithm based ATPG tool. The experimental results on full scan versions of ITC'99 benchmark circuits demonstrate an improvement of the ATPG system both in the number of aborted faults and in test generation time.

Scan based at-speed transition fault testing of Motorola's microprocessors based on the PowerPC/spl trade/ instruction set architecture requires broad-side transition fault test patterns that have a specific launch and capture clocking sequence. We describe the concepts we developed and incorporated in the ATPG tool to support efficient generation of such test patterns to achieve high transition fault test coverage and for analysis of undetected transition faults. Using the enhanced ATPG tool, we generated 15,000 transition fault test patterns and achieved 76% test coverage for the MPC7400 microprocessor based on the PowerPC/spl trade/ instruction set architecture that has 10.5 million transistors and runs at 540 MHz.

Discusses an improved procedure named forward-looking fault simulation. The term forward-looking refers to the fact that certain tests are dropped because they are not necessary for detecting faults that will be detected later in the simulation process. The authors discuss an efficient implementation of forward-looking fault simulation in an industrial environment. They concentrate on reverse order fault simulation. Parallel pattern single fault propagation (PPSFP) simulation is used throughout the implementation of the forward-looking reverse order fault simulation process, since PPSFP is known to result in fast fault simulation for industrial circuits.

A static compaction procedure to reduce test set size for scan designs and a procedure to order test patterns in order to steepen the fault coverage curve are presented. The computational effort for both procedures is linearly proportional to the computational effort required for standard fault simulation with fault dropping. Experimental results on large industrial circuits demonstrate both the efficiency and effectiveness of the proposed procedures.

We propose a new approach for implementing static compaction procedures for synchronous sequential circuits. The procedures we consider belong to the class of procedures that generate the compacted test sequence through restoration of segments (or subsequences) of a given test sequence T. Under the proposed approach, each restored segment detects a single target fault chosen from the faults detected by T at one time unit. A novel parallel pattern simulator is developed for this purpose. Experimental results for benchmark circuits are included.

In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops.

New techniques are presented in this paper to improve the efficiency of a test generation procedure for synchronous sequential circuits. These techniques aid the test generation procedure by reducing the search space, carrying out non-chronological backtracking, and reusing the test generation effort. They have been integrated into an existing sequential test generation system MIX to constitute a new system, named MIX-PLUS. The experimental results for the ISCAS-89 and ADDENDUM-93 benchmark circuits demonstrate the effectiveness of these techniques in improving the fault coverage and test generation efficiency.

We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The procedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.

We describe a time-efficient procedure for identifying undetectable and redundant faults in a synchronous sequential circuit, without using a sequential circuit test pattern generator. The proposed procedure is based on the use of a limited length iterative logic array model of the circuit, and has two phases. In the first phase, faults that will not be proved to be undetectable are identified. In the second phase, undetectable faults are identified out of the remaining faults using a combinational circuit test generator. Sequential static learning on the fault-free circuit and a subset of unreachable states are used in the proposed procedure to increase the amount of information available when considering an iterative logic array model of limited length. An undetectable fault in a synchronizable circuit that leaves the faulty circuit synchronizable is identified as a redundant fault. Experimental results presented in this work demonstrate the effectiveness of the proposed techniques in finding undetectable and redundant faults. Larger numbers of undetectable and redundant faults are found compared to earlier works.

We describe a time-efficient procedure for removing sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use the properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit. By removing several redundant faults simultaneously, the number of repetitions of the test generation procedure invoked to identify redundant faults is reduced. Experimental results presented in this work demonstrate the effectiveness of the proposed removal procedure.