This paper presents a lookup table-based dot product approximation (LDA) for energy-efficient convolutional neural network (CNN) inference as another computing-in-memory (CIM) technique. Using the proposed LDA, computations of CNN can be performed without multiplications; however nearest neighbor search (NNS) is required, resulting in a large energy overhead. To overcome this issue, we propose a time-domain associative memory (TAM) that allows energy-efficient NNS. When the proposed LDA is applied to CNN, the inference accuracy decreases, because LDA involves an approximate computation. To resolve this accuracy degradation, training methods for the LDA-based CNN are proposed. The proposed LDA-based CIM macro using TAM is fabricated in a 65 nm CMOS process. Measurement results indicate that TAM consumes less energy than previously reported associative memory. Owing to the energy-efficient TAM, the LDA-based CIM macro can achieve an energy efficiency of 138 TOPS/W, which is 7.5 times higher than those of the conventional CIM macros fabricated in the same process node.

In this paper, we propose a CMOS current comparison circuit operating at cryogenic temperature to readout spin quantum bit (qubit) states via a charge sensing scheme. A current integrator and correlation double sampling circuit are implemented in the proposed current comparator since precise current sensing is required to achieve readout the states of qubits. The measurement results indicate the feasibility that the reduced readout time by a factor of 1/100 and 100-times better current resolution with the readout fidelity of 99.9 % compared to the conventional readout systems are achieved. Additionally, the current and noise specifications for a charge sensor required to attain it are discussed. Furthermore, the proposed current comparator attains the best tradeoff among power, current resolution, and readout time, compared with the conventional cryogenic current readout circuits.

We propose a 9-bit floating point format for training image-classifier deep convolutional neural networks. The proposed floating point format has a 5-bit exponent, a 3-bit mantissa with the hidden most significant bit (MSB), and a sign bit. The 9-bit floating point format reduces not only the transistor count of the multiplier in the multipy-accumulate (MAC) unit, but also the data traffic for the forward and backward propagations and the weight update. Both of the reductions realize a power efficient training. To maintain the validation accuracy, the accumulator is implemented with an internal longer-bit-length floating point format while the multiplier accepts the 9-bit format. We examined this format in the training of the AlexNet and the ResNet-50 with the ILSVRC 2012 data set. The trained 9-bit AlexNet and ResNet-50 exhibited the validation accuracy superior to the 16-bit floating point format training by 1.2 % and 0.5 %, respectively. The transistor count in the 9-bit MAC unit is estimated to be reduced by 84% as compared to the 32-bit counterpart.

In this paper, a closed-form expression for estimating the minimum operating voltage ($V_{\mathrm{ DDmin}}$) of D flip-flops (FFs) is proposed.$V_{\mathrm{ DDmin}}$is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that$V_{\mathrm{ DDmin}}$of FFs is a linear function of the square root of logarithm of the number of FFs, and its slope depends on the within-die variation of the threshold voltage ($V_{\mathrm{ TH}}$) and its intercept depends on the balance between nMOS and pMOS, which is mainly due to the die-to-die$V_{\mathrm{ TH}}$variation. The proposed expression of$V_{\mathrm{ DDmin}}$is validated by the simulation results as well as the silicon measurements. Finally, we discuss the dependence of$V_{\mathrm{ DDmin}}$on the device parameters.

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDDscaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDminof FFs is higher than the optimum supply voltage. In HVFF, the VDDof combinational logic gates is reduced below the VDDminof FFs while keeping the VDDof FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using “canary flip-flop (FF),” which can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65-nm CMOS process. Measurement results show that the adaptive control can compensate process, supply voltage, and temperature variations and improve the energy efficiency of subthreshold circuits by up to 46% compared to worst-case design and operation with guardbanding. We also discuss how to determine design parameters, such as the inserted location and the buffer delay of the canary FF, supposing two approaches: configuration in the design phase and post-silicon tuning.

New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65 nm 1.2V CMOS process. Seven types of standard cells are measured with 60 DUTs for each type. Good correlations of within-die delay distributions between measured and Monte Carlo simulated results are observed. The measured results of rising and falling delay are of great use to the modeling of standard cell library of deep-submicrometer process. By virtue of the proposed scheme, the relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.

This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using ¿canary flip-flop¿ that can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65 nm CMOS process. Measurement results show that the adaptive control can reduce the power dissipation by 46% in comparison with the worst-case design with guardbanding.

This paper presents transistor variability modeling and its validation for body-biased subthreshold circuits based on measurements of a device-array circuit using a 90-nm technology. The device array consists of p/nMOS transistors and ring oscillators. We examine and confirm the correlation between the performance variation model extracted from measured I-V characteristics and fabricated oscillation frequencies. We demonstrate that delay variations in subthreshold circuits are well characterized with two parameters, i.e., threshold voltage and subthreshold swing parameter. We also reveal that threshold voltage shift by body biasing can be deterministically modeled and statistical modeling is less meaningful.

Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.

Body-biasing is expected to be a common design technique, then area efficient implementation in layout has been demanded. Body-biasing outside standard cells is one of possible layouts. However in this case body-bias controllability, especially when forward bias is applied, is a concern. To investigate the controllability, we fabricated a ring oscillator in a 90nm technology, and measured the controllability. Our measurement result and evaluation of area efficiency reveal that body-biased circuits can be implemented with area overhead of less than 1% yet with sufficient speed controllability.

This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on measurement of a device array circuit in a 90nm technology. The device array consists of P/NMOS transistors and ring oscillators. This work verifies the correlation between the variation model extracted from IV measurement results and oscillation frequencies, which means the transistor-level variation model is examined and confirmed in terms of circuit performance. We demonstrate that delay variations of subthreshold circuits are well characterized with two parameters - threshold voltage and subthreshold swing parameter. We reveal that body bias effect is a less statistical phenomenon and threshold voltage shift by body biasing can be modeled deterministically.