Demo Data from EDBT 2026 / reviewers in the wild / expert
Gabriel Rivera
dblp:77/3687
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 76% High-performance computing · 24% | |
| Software engineering, system software, and programming languages
3 papers |
Compilers and program optimization · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › memory optimization
data locality optimization |
0.1 | 2 | 2000 | Tiling Optimizations for 3D Scientific Computations · SC 2000 Locality Optimizations for Multi-Level Caches · SC 1999 |
Memory systems
cache |
0.0 | 2 | 1999 | Locality Optimizations for Multi-Level Caches · SC 1999 Data Transformations for Eliminating Conflict Misses · PLDI 1998 |
Compilers and program optimization › loop optimization
loop tiling |
0.0 | 1 | 2000 | Tiling Optimizations for 3D Scientific Computations · SC 2000 |
High-performance computing
scientific computing systems |
0.0 | 1 | 2000 | Tiling Optimizations for 3D Scientific Computations · SC 2000 |
Memory systems › cache
conflict miss reduction |
0.0 | 1 | 1999 | Locality Optimizations for Multi-Level Caches · SC 1999 |
Compilers and program optimization › memory optimization
data layout optimization |
0.0 | 1 | 1998 | Data Transformations for Eliminating Conflict Misses · PLDI 1998 |
Memory systems › cache › cache miss
cache conflict misses |
0.0 | 1 | 1998 | Data Transformations for Eliminating Conflict Misses · PLDI 1998 |
Methods — techniques the papers use, named apart from their topics
performance measurement · 0.1cost modeling · 0.1loop fusion · 0.0array padding · 0.0intra-variable padding · 0.0inter-variable padding · 0.0euclidean algorithm for gcd · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Tiling Optimizations for 3D Scientific ComputationsabstractCompiler transformations can significantly improve data locality for many scientific programs. In this paper, we show iterative solvers for partial differential equations (PDEs) in three dimensions require new compiler optimizations not needed for 2D codes, since reuse along the third dimension cannot fit in cachefor larger problem sizes. Tiling is a program transformation compilers can apply to capture this reuse, but successful application of tiling requires selection of non-conflicting tiles and/or padding array dimensions to eliminate conflicts. We present new algorithms and cost models for selecting tiling shapes and array pads. We explain why tiling is rarely needed for 2D PDE solvers, but can be helpful for 3D stencil codes. Experimental results show tiling 3D codes can reduce miss rates and achieve performance improvements of 17-121% for key scientific kernels, including a 27% average improvement for the key computational loop nest in the SPEC/NAS benchmark MGRID. Gabriel Rivera, Chau-Wen Tseng |
SC | 1 |
| 1999 | A Comparison of Compiler Tiling Algorithms
Gabriel Rivera, Chau-Wen Tseng |
CC | 1 |
| 1999 | Locality Optimizations for Multi-Level CachesabstractCompiler transformations can significantly improve data locality of scientific programs. In this paper, we examine the impact of multi-level caches on data locality optimizations. We find nearly all the benefits can be achieved by simply targeting the L1 (primary) cache. Most locality transformations are unaffected because they improve reuse for all levels of the cache; however, some optimizations can be enhanced. Inter-variable padding can take advantage of modular arithmetic to eliminate conflict misses and preserve group reuse on multiple cache levels. Loop fusion can balance increasing group reuse for the L2 (secondary) cache at the expense of losing group reuse at the smaller L1 cache. Tiling for the L1 cache also exploits locality available in the L2 cache. Experiments show enhanced algorithms are able to reduce cache misses, but performance improvements are rarely significant. Our results indicate existing compiler optimizations are usually sufficient to achieve good performance... Gabriel Rivera, Chau-Wen Tseng |
SC | 1 |
| 1998 | Eliminating Conflict Misses for High Performance ArchitecturesabstractMany cache misses in scientific programs are due to conflicts caused by limited set associativity. Two data-layout transformations, inter- and intra-variable padding, can eliminate many conflict misses at compile time. We present GroupPad, an inter-variable padding heuristic to preserve group reuse in stencil computations frequently found in scientific computations. We show padding can also improve performance in parallel programs. Our optimizations have been implemented and tested on a collection of kernels and programs for different cache and data sizes. Preliminary results demonstrate GroupPad is able to consistently preserve group reuse among the programs evaluated, though execution time improvements are small for actual problem and cache sizes tested. Padding improves performance of parallel versions of programs approximately the same magnitude as sequential versions of the same program. 1 Introduction Effectively exploiting caches is widely regarded as the key to achieving good... Gabriel Rivera, Chau-Wen Tseng |
International Conference on Supercomputing | 1 |
| 1998 | Data Transformations for Eliminating Conflict MissesabstractMany cache misses in scientific programs are due to conflicts caused by limited set associativity. We examine two compile-time data-layout transformations for eliminating conflict misses, concentrating on misses occuring on every loop iteration. Inter-variable padding adjusts variable base addresses, while intra-variable padding modifies array dimension sizes. Two levels of precision are evaluated. PADLITE only uses array and column dimension sizes, relying on assumptions about common array reference patterns. PAD analyzes programs, detecting conflict misses by linearizing array references and calculating conflict distances between uniformly-generated references. The Euclidean algorithm for computing the gcd of two numbers is used to predict conflicts between different array columns for linear algebra codes. Experiments on a range of programs indicate PADLITE can eliminate conflicts for benchmarks, but PAD is more effective over a range of cache and problem sizes. Padding reduces cache miss rates by 16% on average for a 16K direct-mapped cache. Execution times are reduced by 6% on average, with some SPEC95 programs improving up to 15%. Gabriel Rivera, Chau-Wen Tseng |
PLDI | 1 |