This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current ($I_{\mathrm {L,DC}}$) compared to the existing single-inductor two-flying-capacitor ($1L$-$2C_{\mathrm {F}}$) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200$\text{m}\Omega $.

This paper presents the design challenges and advanced circuit techniques of integrated gate drivers for non-isolated buck converters using gallium nitride (GaN) devices to achieve fast switching and high conversion efficiency. Focusing on the essential tradeoff considerations, we first explain the detailed circuit-level issues of realizing normal and safe operations regarding integration feasibility, device safety, operation reliability, and power-stage loss alleviation when driving a GaN switch. Accordingly, we review the state-of-the-art techniques for improving various aspects of the performance, including on-chip bootstrapping enhancement, over-voltage and false-switching prevention, electromagnetic interference (EMI) noise suppression, and adaptive driving optimization. We further highlight the feature advantage of distinct techniques in specific performance/function aspects, aiming to bring GaN driver design insights and providing technical references regarding the technical superiority and limitations of improving the overall converter performance.

This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of$6845\mu \text{m}^{2}$. Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across$1.06\sim 1.55V$and$- 30\sim 125^{\circ }\text{C}$, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using$80\times 80\times 80$artificial neural network (ANN) with 1M CPRs as training set.

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50$\text{k}\Omega $load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a$\sim 1.6\times $improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme.

In this paper, a new VCO-assisted VCO-based sigma-delta (ΣΔ) modulator is proposed to improve the linearity of the VCO-based quantizer. The assistant network in the digital feedforward path reduces the input swing of the VCO-based quantizer in the main path, and then adds it together through the digital cancellation path to keep the same signal before and after quantization. Moreover, the merit of the auxiliary VCO increases the tolerance to DAC mismatches because of its intrinsic DEM function, which also simplifies the digital circuit part. A first order continuous-time (CT) ΣΔ modulator with the proposed structure is designed and simulated in a 65nm CMOS process. The performance of the modulator can reach 76.6dB/82.4dB SNDR/SNR with second order noise shaping and 84dB DR within a 10MHz bandwidth and a sampling frequency of 1.4GHz, consuming 9.4mW of power.

A novel structure of VCO-based quantizer for CT ΣΔ modulator is presented which can significantly improve the VCO linearity. Compared to the traditional methods, the proposed structure uses only one VCO in the system and it also maintains the intrinsic Dynamic Element Matching (DEM) function of the VCO-based quantizer. A first order CT ΣΔ modulator with the proposed quantizer is designed and simulated in a 65nm CMOS process. The DAC of the ΣΔ modulator is optimized, which can also save half of the DAC cells. The performance of the modulator can reach 69/67 dB SNR/SNDR and a dynamic range of 78 dB with a bandwidth of 10MHz at 1V supply voltage.