Route optimization (RO) is an important feature of the Electric Vehicles (EVs) which is responsible for finding optimized paths between any source and destination nodes in the road network. In this paper, the RO problem of EVs is solved by using the Multi Constrained Optimal Path (MCOP) approach. The proposed MCOP problem aims to minimize the length of the path and meets constraints on total travelling time, total time delay due to signals, total recharging time, and total recharging cost. The Penalty Function method is used to transform the MCOP problem into unconstrained optimization problem. The unconstrained optimization is performed by using a Particle Swarm Optimization (PSO) based algorithm. The proposed algorithm has innovative methods for finding the velocity of the particles and updating their positions. The performance of the proposed algorithm is compared with two previous heuristics: H_MCOP and Genetic Algorithm (GA). The time of optimization is varied between 1 second (s) and 5s. The proposed algorithm has obtained the minimum value of the objective function in at-least 9.375% more test instances than the GA and H_MCOP.

Article Free Access Share on Cooperative approach to a practical analog LSI layout system Authors: Masato Mogaki View Profile , Youichi Shiraishi View Profile , Mitsuyuki Kimura View Profile , Tetsuro Hino View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 544–549https://doi.org/10.1145/157485.165027Online:01 July 1993Publication History 4citation149DownloadsMetricsTotal Citations4Total Downloads149Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Three kinds of feedthrough assignment algorithm are suggested for CMOS logic cell layout, and their solutions and processing times are compared. One is based on the idea that the feedthrough requirement with fewest feedthrough candidates is first assigned. The second is an optimum algorithm that solves the problem by formalizing it as an integer programming problem. The third is a combination of the two, in which the first algorithm is applied until all of the uniquely determined feedthroughs are assigned, and then the second one is applied. The second and third algorithms attain the optimum solution, but the first one does- not. The deviation of the first algorithm from the optimum solution is shown to be within 3.5% of the optimum. and the cell area increases less than 3.5%. The processing times of the first and third algorithms are 1/27.5 and 1/3.0, respectively, on average, of that of the optimum one. Thus it is concluded that the first algorithm, although not optimum, is practical, and may well be incorporated into the feedthrough assignment process.>

Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI. In the layout of an analog module, a grid-free technique is required to minimize the module area and geometric constraint observance is necessary for the circuit performance optimization. The placement algorithm determines cell positions observing the geometric constraints by vertex-grouping of the constraint graph representing the relative device positions in the input circuit diagram. The routing algorithm, based on the characteristic fine-grid maze router, allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition. These algorithms are applied to the design of the analog modules. Automatically designed modules are compact and the performance requirements are met.>

A permeation routing algorithm is proposed which decides the detailed routes on a new layout model. The permeation router attains a higher density by using the expanded routing region as well as the conventional one simultaneously. This routing algorithm consists of two phases. One is to partition the trunk set into three subsets corresponding to the trunks to be routed in the channel on the lower transistor row, upper transistor row, or between transistor rows. The other is to route these channels by using the one-layer channel assignment method as well as the conventional one. The experiments show that the routing results are practical and that the processing time is proportional to the number of trunks to the power of 1.4.

Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement with “scope” and “zone”, which are new concepts representing limits, and an iterative weighted improvement method are presented. Such algorithms are applied to hundreds of 2 K and 5 K gate ECL masterslice LST's for a newly developed high-end mainframe computer, the Hitachi M-680H. Through such algorithms, the physical design is greatly improved by guaranteeing high wirability and improving electrical characteristics.