Shingled Magnetic Recording (SMR) disks have been improved significantly over traditional Hard Disk Drives (HDDs) in storage capacity and cost by a shingled-like structure that overlaps with adjacent tracks. However, the overall system performance is severely sacrificed due to the large portion of Read-Merge-Write (RMW) operations triggered by the non-sequential nature of SMR disks. To handle such performance degradation, Persistent Cache (PC) and built-in NAND flash cache are applied to absorb non-sequential writes. However, when the cache is full, triggering write-back operations extends the I/O response time. Additionally, the erase of NAND flash also compromises its lifetime.This paper aims to manage the NAND flash region and the original SMR band region uniformly instead of only adopting NAND flash as a cache layer. To achieve this, we propose a Region-based Co-optimized strategy named Multi-Regional Collaborative Management (MCM). Our approach segments I/O requests using a fast and efficient Bloom filter alongside a Band-based partitioning module. Additionally, the NAND flash memory region is managed based on the characteristics of the segmented data, enabling maximum control over frequent data updates in the NAND flash memory. The NAND flash cache will not serve as the first-level cache as before. Meanwhile, through Region-aware Wear-leveling (WL) and garbage collection (GC) strategies, the lifetime of NAND flash memory is extended, and cleaning efficiency is improved. In addition, further analysis of the impact of the wear-leveling parameters on RMWs and NAND flash lifetime under different workloads. According to the experimental results, compared with the typical Skylight (baseline), our scheme reduces the average response time and write amplification by 74.56% and 98.99%, respectively. At the same time, our approach also outperforms some state-of-the-art solutions, such as MU-RMW, RMW-F, and FC.

In SSD-SMR hybrid storage systems, the Persistent Cache (PC) cleaning process in Shingled Magnetic Recording (SMR) disks involves frequent Read-Modify-Write (RMW) operations, significantly increasing system tail latency. Although traditional Q-learning methods alleviate this issue to some extent, the expansion of state space results in an increase in the dimensions of the Q-Table, leading to significant rises in computational and storage costs, thus limiting its ability to handle complex problems. In this paper, we propose an intelligent data prediction management strategy named Augur, based on Deep Reinforcement Learning (DRL), that predicts nodes where high latency is imminent and directs the agent named Pythia to timely redirect the flow of suspect data, effectively reducing RMW operations in SMR. We implement our technique on a real SSD-SMR hybrid storage system. Experimental results show that, compared to Q-learning and Skylight, our method reduces the system tail latency at the 99.9thpercentile by 23.61% and 58.35%, and reduces average request latency by 22.54% and 47.56%, respectively.

The frequent Read-Modify-Write operations (RMWs) in Shingled Magnetic Recording (SMR) disks severely degrade the random write performance of the system. Although the adoption of persistent cache (PC) and built-in NAND flash cache alleviates some of the RMWs, when the cache is full, the triggered write-back operations still prolong I/O response time and the erasure of NAND flash also sacrifices its lifetime. In this paper, we propose a Region-based Co-optimized strategy named Multi-Regional Collaborative Management (MCM) to optimize the average response time by separately managing sequential/random and hot/cold data and extend the NAND flash lifetime by a region-aware wear-leveling strategy. The experimental results show that our MCM reduces 71 % of the average response time and 96% of RMWs on average compared with the Skylight (baseline). For the comparison with the state-of-art flash-based cache (FC) approach, we can still save the average response time and flash erase operations by 17.2 % and 33.32 %, respectively.

A 600-Mb/s rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder was implemented in a 90-nm CMOS process. The encoder operates at 1.1 GHz and includes built-in all-phase termination. The decoder design maximizes throughput while minimizing the number of memory banks and delivering an information throughput of 1 bit per clock cycle. The size of the decoder controller is minimized by sharing it among an arbitrary number of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2.0 and a throughput of 600 Mb/s. An integrated test system enables accurate power measurements for various SNR settings.

Low-density parity-check convolutional codes (LDPC-CCs) have been shown to have similar capacity-approaching performance to LDPC block codes. Their encoder structure is simple and efficient. However, the encoder termination, which is required when applied to finite length data frames, increases the encoder complexity and reduces the effective code rate. The LDPC-CC encoding and termination problems are discussed in this paper. A novel all-phase termination scheme is proposed with less implementation complexity and less loss in code rate, compared to existing methods. Finally a system architecture for the LDPC-CC encoder with all-phase termination is given with some analyses.

Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and decode arbitrary lengths of data. This makes these codes well suited to certain applications, such as forward error control on packet switching networks. In this paper we propose a decoder architecture for low-density parity-check convolutional codes with very large memories. These codes have very good error correcting properties and as such may be applicable in wireless sensor networks and space communication systems. We discuss a realization of this architecture for a (2048,3,6) code implemented on a field-programmable gate-array.

In this paper, the application of low-density parity-check convolutional codes (LDPC-CCs) to packet based communication systems is studied. By presenting analysis of encoder and decoder design as well as simulation results for such systems, we show that LDPC-CCs are more suited to packet based applications than LDPC block codes (LDPC-BCs). This is due to their ability to operate on arbitrary lengths of data, lower encoder complexity and the performance gain of presetting and termination. Moreover, in this paper, we propose an algorithm for terminating the LDPC-CC encoder from any state to the all-zero state.

In OCR systems the character segmentation algorithm may generate mis-segmented blocks. Feedback information from character classifier is indispensable to achieve higher character segmentation accuracy. In this paper a novel rejection algorithm is proposed to identify these mis-segmented characters more accurately. First, based on confidence evaluation of distance-based classifiers, the usual generalized confidence mapping function is modified to fit this specific purpose. Second, a novel adaptive thresholding rejection rule is proposed, which is more accurate and flexible. Experiments on Chinese, Japanese and Korean document recognition showed that new rejection algorithm evidently improved the system performance, especially for low-quality printed document recognition. 1.

In the traditional DKL algorithm, PCA is performed before LDA to achieve stable numerical computation and good generalization in small-sample-size problems. However, PCA is based on the global information, ignoring the significant local characteristics. This paper will propose a novel algorithm called discriminant local feature analysis based on a broader understanding of LFA features. In the algorithm, LFA instead of PCA is applied before LDA. On the one hand, LFA captures local characteristics with little loss of global information. On the other hand, it presents an effective low-dimensional representation of signals, and thus reduces the dimensionality for LDA. By combining LFA and LDA, the DLFA algorithm outperforms DKL, which is showed by experiments on open-set face verification.