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Masaki Itoh

dblp:77/5110 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Interconnection networks and networks-on-chip · 100%
Software engineering, system software, and programming languages
1 paper
Program verification · 87% Requirements engineering and software design · 13%
Theoretical computer science
2 papers
Graph algorithms and graph theory · 100%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology
low-diameter topology
0.021983
A Design for Directed Graphs with Minimum Diameter · IEEE Trans. Computers 1983
Design to Minimize Diameter on Building-Block Network · IEEE Trans. Computers 1981
Interconnection networks and networks-on-chip
network topology
0.021983
A Design for Directed Graphs with Minimum Diameter · IEEE Trans. Computers 1983
Design to Minimize Diameter on Building-Block Network · IEEE Trans. Computers 1981
Program verification › model checking › state space exploration
reachability analysis
0.011985
Specification and Verification of Switching Software · IEEE Trans. Commun. 1985
Program verification
specification verification
0.011985
Specification and Verification of Switching Software · IEEE Trans. Commun. 1985

Methods — techniques the papers use, named apart from their topics

graph design procedure · 0.0graph design algorithm · 0.0state transition machine · 0.0reachability tree analysis · 0.0
YearPublicationVenuePosition
1991 SDE: Incremental Specification and Development of Communications Software
abstract
A technique for applying formal message sequence specifications to the full definition of systems is presented. The technique supports automatic transformation of message sequence descriptions into communicating process descriptions that implement the sequences. It also supports hierarchical verification of protocols in the message sequences and process descriptions. Both a language for message sequence description, SAL, and a design support environment, SDE, have been developed based on the proposed technique. To collectively and hierarchically describe message sequences, SAL can compose message sequences from message sequence elements. By adding SAL descriptions, SDE supports the incremental specification and development of communications software: consistency between the added sequences and existing software is verified, and the existing software is automatically updated. This support especially contributes to the efficient maintenance of communications software. The feasibility and usefulness of the proposed technique are demonstrated by experimental application of SDE to PBX.>
Haruhisa Ichikawa, Masaki Itoh, June Kato, Akira Takura, Masashi Shibasaki
IEEE Trans. Computers2
1985 Specification and Verification of Switching Software
abstract
This paper describes specification and verification technology for software development. This technology consists of 1) a Specification description language called LAN-S, 2) a compiler to generate data for specification verification, and 3) a specification analysis algorithm (analyzer). A switching system and terminals are regarded as state transition machines in this technology. From specifications described in LAN-S, input data for the specification analyzer are generated. The analyzer incorporates a concept of the reduced reachability tree (RRtree), which can solve the "state space explosion" encountered in the ordinary teachability tree analysis. Using some subprocedure libraries, the switching software specification in LAN-S is transformed into an executable control program for a system with "process based software architecture." When applied to software development for a model switching system SPICE, the analyzer produced a reachability tree smaller than the one produced via the ordinary reachability tree analysis by 99.95 percent, and proved to be applicable to practical systems analysis.
Masaichi Kajiwara, Haruhisa Ichikawa, Masaki Itoh, Yasuyuki Yoshida
IEEE Trans. Commun.3
1983 A Design for Directed Graphs with Minimum Diameter
abstract
This paper proposes a simple procedure for the design of small-diameter graphs. It can be used to construct a directed graph whose diameter is less than or equal to that of any previously proposed graph.
Makoto Imase, Masaki Itoh
IEEE Trans. Computers2
1981 Design to Minimize Diameter on Building-Block Network
abstract
This paper proposes a simple algorithm for the graph design of small-diameter networks. For given nodes n and degree d, this algorithm can be used to construct a directed graph with diameter ⌈logd n⌉, which is at most one larger than the lower bound ⌈logd (n(d − 1) + 1)⌉ − 1. Its average distance is also close to the lower bound. The algorithm can be used to construct a directed graph with smaller diameter, compared with any other conventional methods, when n is larger.
Makoto Imase, Masaki Itoh
IEEE Trans. Computers2