Intermittent systems require software support to execute tasks amid frequent power failures. In designing such techniques, software designers rely on execution models that abstract hardware-level operations. In this paper, we propose an execution model that more accurately describes emerging intermittent systems with small energy storage. Our evaluation shows show that systems designed based on the traditional models can be up to 5.62 x less power-efficient than expected and may result in unsafe checkpoint operations. Our design guidelines enhance the performance of existing static and dynamic checkpoint techniques by 3.04 x and 2.85 x on average, respectively.

Intermittently powered devices, such as batteryless energy harvesting systems, rely on checkpoint and recovery to maintain progress across frequent power failures. Differential checkpointing reduces the high cost of checkpointing by saving only the modified memory regions. Existing hardware-based approaches have presented significant benefits by tracking memory modifications using block-based hardware trackers. On the other hand, they have limited scalability as the hardware cost proportionally increases with memory size, which is critical in recent intermittent systems featuring more resources. Furthermore, their designs only support synchronous checkpointing where the MCU is blocked during the backups, failing to hide huge checkpoint latency. This paper proposes FLASC, a hardware-software co-design which scales with increasing memory size as well as supports safe and efficient asynchronous checkpoint executions. Our evaluations on FPGA show that FLASC achieves 9.4% faster execution while using only 49.1% hardware resource compared to the state-of-the-art, resulting in 1.85x efficiency per hardware resources. Furthermore, FLASC presents 6.9x better scalability with increasing data memory size, effectively addressing the scalability challenge of existing architecture.

Intermittent computing supports task execution amid frequent power failures relying on checkpoints. To minimize checkpoint execution, checkpoint triggers are inserted into the program, with actual execution decided at runtime. Despite these efforts, significant overhead remains from merely invoking checkpoint triggers, especially within loops. We present FastTrack, an approach to reduce redundant checkpoint triggers in static checkpoint schemes. FastTrack generates two versions of the loops in the program, one with checkpoint instrumentation and one without, and execute them selectively at runtime. FastTrack eliminates an average of 98.6% of checkpoint triggers, resulting in more than a 10x improvement in end-to-end latency.

Intermittent computing enables computing under environments that may experience frequent and unpredictable power failures, such as energy harvesting systems. It relies on checkpointing to preserve computing progress between power cycles, which often incurs significant overhead due to energy-expensive writes to Non-Volatile Memory (NVM). In this paper, we present LACT (Liveness-Aware CheckpoinTing), as an approach to reducing the size of checkpointed data by exploiting the liveness of memory objects: excluding dead memory objects from checkpointing does not affect the correctness of the program. Especially, LACT can analyze the liveness of arrays, which take up most of the memory space but are not analyzable by existing methods for detecting the liveness of scalar objects. Using the liveness information of arrays, LACT determines the minimized checkpoint range for the arrays at compile time without any runtime addition. Our evaluation shows that LACT achieves an additional reduction of checkpointed data size of 37.8% on average over the existing state-of-the-art technique. Also, our experiments on a real energy harvesting environment show that LACT can reduce the execution time of applications by 27.7% on average.