Traditionally, logic synthesis/optimization metric would be majorly determined by PPA (power, performance, area). However, as the technology node shrinks and the design process becomes extremely complicated, iterative optimization flow and local re-synthesis might be invoked to optimize for more variant purposes. It is necessary to have a methodology which is not just a simple cost-function-based algorithm but also can optimize and legalize a design according to a more complex cost estimator.

Boolean Matching problem determines whether two Boolean functions are functionally equivalent under the permutation and negation of inputs and outputs. Prior contest [1] has extended the problem to allow inputs binding with constant value and the ports matching can be one-to-many projection. In this contest, we further extended the problem to consider the ports grouping information, which is caused by the buses or datapaths in the modern digital IC design.

Extracting circuit functionality from a gate-level netlist is critical in CAD tools. For security, it helps designers to detect hardware Trojans or malicious design changes in the netlist with third-party resources such as fabrication services and soft/hard IP cores. For verification, it can reduce the complexity and effort of keeping design information in aggressive optimization strategies adopted by synthesis tools. For Engineering Change Order (ECO), it can keep the designer from locating the ECO gate in a sea of bit-level gates.

Functional ECO is an essential solution in the VLSI design flow. The technique is to realize the functional changes with a minimal patch netlist in the gate-level netlist. As the increasing of the design complexity, functional ECO becomes more and more difficult to generate a minimal patch. ICCAD 2021 CAD contest calls for a feasible and efficient ECO algorithm with behavioral change guidance. More than ordinary functional ECO problems, the RTL designs are provided. Contestants can utilize the behavioral change in RTL designs to minimize the patch for G1.

Equivalence checking is the practical industrial solution to sign-off digital functionality for large-scale circuits. However, when design contains implicit and explicit X-values, the complexity of equivalence checking increases and heuristics used in binary-value equivalence checking may not be applicable for X-value equivalence checking. The goal of the ICCAD 2020 CAD contest is to ask the good algorithm and heuristic to solve the X-value equivalence checking. In this contest, we provide the benchmark suites for contestant to evaluate their program. We hope the contest result can improve industry applications and bring more research interests.

Using sampling patterns is always a powerful method to save efforts for the problems with large input space since it can quickly help identify cases' properties. The meaning behind these sampling results can be informative and useful, but these results may be unreadable to humans. Therefore, in 2019 CAD Contest [1], we formulate a problem of “logic regression on high dimensional Boolean space”. Given a blackboxed input-output relation generator, contestants are required to find a minimal Boolean logic circuit which matches the input-output relations of the given generator. In this contest, we provide benchmarks that address industrial applications of logic regression with several scenarios and different scales of input space to evaluate contestants' algorithms. We expect that the contest results can help industrial application and attract interesting academic research.

With a functional Engineering Change Order (ECO) problem, the quality of patch plays an important role in the performance of the patched circuit. In this contest, contestants need to generate patch functions that will make two circuits equivalent, while minimizing the resource cost of the generated patches. Resource cost is the comprehensive physical cost of all the patches, and minimizing the resource cost implies improving patch quality (timing, power, routing, or area). The resource cost of patches can be modeled as a weighting function with respect to several physical properties of nodes used for patches. In ICCAD 2017 CAD Contest, we have assigned each internal node a reasonable constant weight to represent the corresponding physical cost if the node is used for generating patches. Also, the resource cost of the patches is calculated as the weight summation of patches' support nodes. This formulation can elegantly identify wanted algorithms for the resource-aware patch generation problem.

Boolean Matching is significant to industry applications, such as library binding, synthesis, engineer change order, and hardware Trojan detection. Instead of basic Boolean matching, Non-exact Projective NPNP Boolean Matching allows to match two designs by not only negating and permuting inputs/outputs but also merging them or binding constants to inputs. Besides, the matching goal is extended to achieve the largest number of output equivalences between two designs. This kind of Boolean matching may get better quality in the related applications due to more flexibility and scalability, and the development of its algorithms is more challengeable. Hence, this problem has some research values. In ICCAD 2016 CAD contest, given two designs, participants need to decide how to permute, negate and merge designs' inputs/outputs or bind constants for achieving largest number of output equivalences. The score will be evaluated by how many outputs are equivalent and the runtime. We expect the contest result can improve industry applications and bring more research interests.

Equivalence checking (EC) and functional Engineering Change Order (ECO) on large-scale designs becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in how to partition the large-scale problems into smaller EC and ECO problem with lower complexity. In this contest, we ask the participants to design the algorithm to insert the corresponding cuts as the partitioned points on given two designs as simplifying the EC and ECO problems. The team correctly simplifying the problem most wins the contest. The benchmark suites are extracted from the real designs in our interesting applications. We look forward to triggering the academic area to investigate on this problem.

Efficiently solving numerous relevant circuit satisfiability (CircuitSAT) problems becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in: how to select the best setting of the Boolean satisfiability (SAT) solver based on sample problems, and what is the most useful conjunctive normal form (CNF) encoding for some particular designs and particular applications. From practical experience, the run time yielded by solving SAT problems using the default setting is far from best run time; same is true for CNF encoding. In this contest, we ask the participants to design the algorithm for exploring the best setting based on some sample cases, and we determine the contest winners by evaluating the run time for solving the remaining problems. The benchmark suites are extracted from the real designs in our applications of interest. We look forward to triggering the academic area in further investigating this problem.

Interpolation is an important and distinguished method popularly applied to recent synthesis and verification research topics. Existing approaches generate interpolants by analyzing unsatisfiability (UNSAT) proofs from satisfiable (SAT) solvers. Unfortunately, the interpolant is predestinedly determined by how the UNSAT proof is logged. This particularly weakens the abstraction of interpolation-based model checking procedure. In this paper, a new approach to generate a variety of functionally different interpolants using simulation and SAT solving is proposed. We further seamlessly integrated the novel interpolant generation algorithm into a reinterpreted interpolation-based model checking procedure. Moreover, spurious counterexamples from the model checker further guide the generation of interpolants to refute excessive refinements. As an extra benefit, proof logging is not required for SAT solvers. Experiments show promising results of our interpolation-based model checker NewITP on solving a large set of HWMCC benchmarks.

Interpolation is an important and distinguished method popularly applied to recent synthesis and verification research topics. Existing approaches generate interpolants by analysing unsatisfiability proofs from SAT solvers. Unfortunately, the interpolant is predestinedly determined by how the unsatisfiability proof is logged. This particularly weakens the abstraction of interpolation-based model checking procedure. In this paper, a new approach to generate a variety of functionally different interpolants using simulation and SAT solving is proposed. We further seamlessly integrated the novel interpolant generation algorithm into the reinterpreted interpolation-based model checking procedure. Moreover, spurious counterexamples from the model checker further guide the generation of interpolants to refute excessive refinements. As an extra benefit, proof logging is not required for SAT solvers. Experiments show promising results of our interpolation-based model checker NewITP on solving a large set of HWMCC benchmarks.

ECO re-mapping is a key step in functional ECO tools. It implements a given patch function on a layout database with a limited spare cell resource. Previous ECO re-mapping algorithms are based on existing technology mappers. However, these mappers are not designed to consider the resource limitation and thus the corresponding ECO results are generally not good enough, or even become much worse when the spare cells are sparse. In this paper, we proposed a new solution for ECO remapping. It includes a robust resource-constraint-aware technology mapper and a fast incremental router for wire-length optimization. Moreover, we adopt a Pseudo-Boolean solver to search feasible solutions when the spare cells are sparse. Our experimental results show that our ECO engine can outperform the previous tool in both runtime and routing costs. We also demonstrate the robustness of our tool by performing ECOs on various spare cell limitations.

To cope with last-minute design bugs and specification changes, engineering change order (ECO) is usually performed toward the end of the design process. This paper proposes an automatic ECO synthesis algorithm by interpolation. In particular, we tackle the problem by a series of partial rectifications. At each step, partial rectification can reduce the functional difference between an old implementation and a new specification. Our algorithm is especially effective for multiple error circuits. Experimental results show the proposed method is far superior to the most recent work and scales well on a set of large circuits.

Virtual platform simulation is an essential technique for early-stage system-level design space exploration and embedded software development. In order to explore the hardware behavior and verify the embedded software, simulation speed and accuracy are the two most critical factors. However, given the increasing complexity of the Multi-Processor System-on-Chip (MPSoC) designs, even the state-of-the-art virtual platform simulation algorithms may suffer from the simulation speed issue. In this paper, we proposed an Ultra Synchronization Checking Method (USCM) for fast and robust virtual platform simulation. We devise a data dependency table (DDT) so that the memory access information by the hardware modules and software programs can be predicted and checked. By reducing the unnecessary synchronizations among simulation modules and utilizing the asynchronous discrete event simulation technique, we can significantly improve the virtual platform simulation speed. Our experimental results show that the proposed USCM can simulate a 32-processor SoC design in the speed of multimillion instructions per second. We also demonstrate that our method is less sensitive to the number of cores in the virtual platform simulation.

We proposed a novel Boolean Satisfiability (SAT)-controlled redundancy addition and removal (RAR) algorithm to resolve the performance and quality problems of the previous RAR approaches. With the introduction of modern SAT techniques, such as efficient Boolean constraint propagation (BCP), conflict-driven learning, and flexible decision procedure, our RAR engine can identify 10x more alternative wires/gates while achieving 70% reduction in runtime.

In this paper, we proposed a novel interpolant generation algorithm without constructing the resolution graph of the unsatisfiability proof. Our algorithm generates the interpolant by building sub-interpolants from conflict analyses and then merges them based on the last decision conflict. The experimental results show that our algorithm has the advantages over the prior interpolant generation techniques in both memory usage and interpolation circuit size.