Energy efficiency in high performance computing (HPC) will be critical to limit operating costs and carbon footprints in future supercomputing centers. Energy efficiency of a computation can be improved by reducing time to completion without a substantial increase in power drawn or by reducing power with a little increase in time to completion. We present an Adaptive Core-specific Runtime (ACR) that dynamically adapts core frequencies to workload characteristics, and show examples of both reductions in power and improvement in the average performance. This improvement in energy efficiency is obtained without changes to the application. The adaptation policy embedded in the runtime uses existing core-specific power controls like software-controlled clock modulation and per-core Dynamic Voltage Frequency Scaling (DVFS) introduced in Intel Haswell. Experiments on six standard MPI benchmarks and a real world application show an overall 20% improvement in energy efficiency with less than 1% increase in execution time on 32 nodes (1024 cores) using per-core DVFS. An improvement in energy efficiency of up to 42% is obtained with the real world application ParaDis through a combination of speedup and power reduction. For one configuration, ParaDis achieves an average speedup of 11%, while the power is lowered by about 31%. The average improvement in the performance seen is a direct result of the reduction in run-to-run variation and running at turbo frequencies.

As the HPC community moves into the exascale computing era, application energy is becoming as large of a concern as performance. Optimizing for energy will be essential in the effort to overcome the limited power envelope. Existing efforts to optimize energy in applications employ Dynamic Frequency and Voltage Scaling (DVFS) to maximize energy savings in less compute-intensive regions or non-critical execution paths. However, we found that DVFS has high power state switching overhead, preventing its use when a more fine-grained technique is necessary. In this work, we take advantage of the low transition overhead of CPU clock modulation and apply it to fine-grained Open MP parallel loops. The energy behavior of Open MP parallel regions is first characterized by changing the effective frequency using clock modulation. The clock modulation setting that achieves the best energy efficiency is then determined for each region. Finally, different CPU clock modulation settings are applied to the different loops within the same application. The resulting multi-frequency execution of Open MP applications achieves better energy-delay trade-off than any single frequency setting. In the best case scenario, the multi-frequency approach achieved 8.6% energy savings with less than 1.5% execution time increase. Concurrency throttling (i.e., Reducing the number of hardware threads used by an application) saves more energy and can be combined with CPU clock modulation. Using both, we see savings of 21% energy and improvement of energy-delay product (EDP) by 16%.

We present and evaluate a surrogate model, based on hardware performance counter measurements, to estimate computer system power consumption. Power and energy are especially important in the design and operation of large data centers and of clusters used for scientific computing. Tradeoffs are made between performance and power consumption, this needs to be dynamic because activity varies over time. While it is possible to instrument systems for fine-grain power monitoring, such instrumentation is costly and not commonly available. Furthermore, the latency and sampling periods of hardware power monitors can be large compared to time scales at which workloads can change and dynamic power controls can operate. Given these limitations, we argue that surrogate models of the kind we present here can provide low-cost and accurate estimates of power consumption to drive on-line dynamic control mechanisms and for use in off-line tuning.

Multi-core computers are ubiquitous and multi-socket versions dominate as nodes in compute clusters. Given the high level of parallelism inherent in processor chips, the ability of memory systems to serve a large number of concurrent memory access operations is becoming a critical performance problem. The most common model of memory performance uses just two numbers, peak bandwidth and typical access latency. We introduce concurrency as an explicit parameter of the measurement and modeling processes to characterize more accurately the complexity of memory behavior of multi-socket, multi-core systems. We present a detailed experimental multi-socket, multi-core memory study based on the PCHASE benchmark, which can vary memory loads by controlling the number of concurrent memory references per thread. The make-up and structure of the memory have a major impact on achievable bandwidth. Three discrete bottlenecks were observed at different levels of the hardware architecture: limits on the number of references outstanding per core; limits to the memory requests serviced by a single memory controller; and limits on the global memory concurrency. We use these results to build a memory performance model that ties concurrency, latency and bandwidth together to create a more accurate model of overall performance. We show that current commodity memory sub-systems cannot handle the load offered by high-end processor chips.

Many programs exploit shared-memory parallelism using multithreading. Threaded codes typically use locks to coordinate access to shared data. In many cases, contention for locks reduces parallel efficiency and hurts scalability. Being able to quantify and attribute lock contention is important for understanding where a multithreaded program needs improvement.

MAESTRO is a prototype runtime designed to provide simple, very light threads and synchronization between those threads on modern commodity (times86) hardware. The MAESTRO threading library is designed to be a target for a high-level language compiler or source-to-source translator, not for user-level programming. It provides parallel programming environments with a straight forward hardware model which can be mapped to available hardware dynamically. MAESTRO separates the size of the hardware system being used from the amount of parallelism available in an application. By separating the problem of locating parallelism from the problem of effectively using parallelism, both problems can be made easier. To the extent possible, the programming environment should be responsible for finding parallelism and the runtime should manage resource allocation and assignment. Parallel regions and parallel loops are implemented. Several simple benchmarks have been ported from OpenMP to use the MAESTRO threading interface. Two synchronization mechanisms have been implemented, one for general synchronization and one for producer-consumer relationships. We have started building a level of 'virtualization' between the programming environment and the actual hardware, which will allow better hardware utilization and support new parallel programming languages.

This paper describes an integrated architecture, compiler, runtime, and operating system solution to exploiting heterogeneous parallelism. The architecture is a pipelined multi-threaded multiprocessor, enabling the execution of very fine (multiple operations within an instruction) to very coarse (multiple jobs) parallel activities. The compiler and runtime focus on managing parallelism within a job, while the operating system focuses on managing parallelism across jobs. By considering the entire system in the design, we were able to smoothly interface its four components. While each component is primarily responsible for managing its own level of parallel activity, feedback mechanisms between components enable resource allocation and usage to be dynamically updated. This dynamic adaptation to changing requirements and available resources fosters both high utilization of the machine and the efficient expression and execution of parallelism.

Article Software prefetching Share on Authors: David Callahan View Profile , Ken Kennedy View Profile , Allan Porterfield View Profile Authors Info & Claims ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systemsApril 1991 Pages 40–52https://doi.org/10.1145/106972.106979Online:01 April 1991Publication History 394citation1,868DownloadsMetricsTotal Citations394Total Downloads1,868Last 12 Months79Last 6 weeks7 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Free Access Share on The Tera computer system Authors: Robert Alverson Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , David Callahan Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Daniel Cummings Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Brian Koblenz Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Allan Porterfield Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Burton Smith Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile Authors Info & Claims ICS '90: Proceedings of the 4th international conference on SupercomputingJune 1990 Pages 1–6https://doi.org/10.1145/77726.255132Online:01 June 1990Publication History 553citation2,281DownloadsMetricsTotal Citations553Total Downloads2,281Last 12 Months382Last 6 weeks81 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The data cache performance of a set of computationally intensive programs is examined. The measurement of cache performance arises from an interest in improving the performance of a program during compilation. It was observed that the data caches contained the values for between 45% and 99+% of the array access, depending on the cache and the program. The delays from the misses accounted for up to half of the total execution time of the program. The misses were grouped in a subset of source program references which resulted in misses on every access. It is pointed out that aggressive compilers should be able to improve program performance by focusing on those array accesses that result in cache misses.>