In this work, we propose a method for detection of locations with subjective significance in the visual environment using Information Constrained Control (ICC). ICC is a model that takes into consideration not only the goal but also the complexity of the control needed to achieve it, characterized by its deviation from default behavior. This concept resonates with the human visual attention system, which includes an interaction between top-down goal oriented pressure and bottom-up processes of common gaze behavior. We start by providing rationale and intuition for ICC based analysis, then formalize it. Specifically, we formalize a mechanism for estimation of subjective significance. Later, we theoretically compare the ICC to the commonly used STD based mechanism, present the latter as a special case of ICC, suggesting an ICC reward visualization mechanism for STD. Finally, we describe our experiment in a real-world driving environment and present empirical finding to support our claim.

Seat belt routing classification is of crucial importance to the automotive industry. It determines whether an occupant's seat belt is not only buckled but also properly routed through the body, making sure that the occupant is truly protected in case of an accident. Current technology, such as the buckle Hall effect sensor, only addresses the problem of buckling detection, but no reliable solution exists for the proper routing scenario. In this work we compiled a database of more than 34,000 images each from two different camera setups and trained deep neural networks to detect improper seat belt routing. The results show that the best camera setup can achieve an accuracy of 0.977 on a coarse (four-class) wrong routing classification task and 0.924 on a fine-grained (seven-class) classification task, which may be a step toward reducing injuries.

We explore the feasibility of measuring learner engagement and classifying the engagement level based on machine learning applied on data from 2D/3D camera sensors and eye trackers in a 1:1 learning setting. Our results are based on nine pilot sessions held in a local high school where we recorded features related to student engagement while consuming educational content. We label the collected data as Engaged or NotEngaged while observing videos of the students and their screens. Based on the collected data, perceptual user features (e.g., body posture, facial points, and gaze) are extracted. We use feature selection and classification methods to produce classifiers that can detect whether a student is engaged or not. Accuracies of up to 85-95% are achieved on the collected dataset. We believe our work pioneers in the successful classification of student engagement based on perceptual user features in a 1:1 authentic learning setting.

In general, we lack in EDA industry tools and automated solutions in μArchitectural domain. In this paper, we elaborate on our attempt to advance performance simulation based statistical analysis techniques. On one hand, we utilize the content knowledge of μArchitectural specification (e.g., explicit specification of the major transactions), and on the other hand, the statistical compact representation of the simulation trace. We name the compact statistical modeling of transaction level performance simulation traces, Magenta (Modeling Agent for Transactional Analysis). As demonstrated by industrial case studies, Magenta can effectively capture all the sample flows that are represented in the simulation trace that exhibit the transaction of interest in terms of μArchitectural events in a statistical event dependency graph. Our industrial experience shows that Magenta is an effective statistical model for μArchitectural performance verification and power/performance trade-off.

To provide higher performance by staying within a constant power budget is challenging. Today, operational cost and specifically energy cost constitute a large portion of an organization's Total Cost of Ownership (TCO), so it is crucial that microprocessor consumes the lowest possible power for a given workload. In this paper, we describe the major challenges faced by the microprocessor architects in achieving higher performance within constant power budget or energy-efficiency, with special focus on design technologies and solutions. We present a die level power simulation solution that facilitates exploration of system-level power management algorithms that budget power for various microprocessor die components. We demonstrate usage methodology via real-life use case studies and recommend future areas of research that can enhance the proposed power management simulation methodology.

Adopting an ESL based design and validation methodology, we introduce a top-down approach for efficient debugging of microarchitectural specification and RTL implementation. Our solution is based on the formalism introduced by statistical transactional analysis that we call MAGENTA -- Modeling AGENT for Transactional Analysis. To the best of our knowledge, MAGENTA based root-cause analysis pioneers in the efficient characterization of the micro-architectural design misbehavior via abstraction of validation output by transactions and micro-architectural events.

Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating conditions for blocks that are poorly gated or not gated at all. A second contribution of our paper is a robust and scalable approach to extract stability conditions for clock gating. Finally, we present a uniform treatment of unobservability and stability as dual approaches for propagating gating conditions forward and backward. Experimental results demonstrate significant power reduction (in the range of 14% -- 55% of the clock power) on Intel micro-processor designs.

We describe a general approach for defining new temporal specification languages, and adopting existing languages, for SystemC. We define the concept of "underlying trace" describing the execution of a SystemC model, and then define a set of important primitive assertions about the states in the trace. Our framework not only provides additional expressive power for making atomic assertions, but also provides very fine control over the temporal resolution of the language. Using the primitives defined here as clock expression allows sampling at different levels, from transaction-level to the level of individual statements. The advantage of our approach is that it defines important SystemC properties that have been overlooked previously, and also provides a uniform mechanism for specifying the sampling rate of temporal languages.

One method of handling the computational complexity of the verification process is to combine the strengths of different approaches. We propose a hybrid verification technology combining symbolic trajectory evaluation with either symbolic model checking or SAT-based model checking. This reduces significantly the cost (both human and computing) of verifying circuits with complex initialisation, as well as simplifying proof development by enhancing verification productivity. The approach has been tested on current Intel designs.

Article Free Access Share on Adaptive variable reordering for symbolic model checking Authors: Gila Kamhi Future CAD Technologies, Intel Israel Ltd., P.O. BOX 1659, Haifa, Israel Future CAD Technologies, Intel Israel Ltd., P.O. BOX 1659, Haifa, IsraelView Profile , Limor Fix Future CAD Technologies, Intel Israel Ltd., P.O. BOX 1659, Haifa, Israel Future CAD Technologies, Intel Israel Ltd., P.O. BOX 1659, Haifa, IsraelView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 359–365https://doi.org/10.1145/288548.289054Published:01 November 1998Publication History 12citation224DownloadsMetricsTotal Citations12Total Downloads224Last 12 Months10Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF