Recently, low-power and wide area (LPWA) network is one of the hottest wireless technologies to realize low-cost Internet of things (IoT) systems. Many proprietary LPWA schemes have been actively developed, some of which have been utilized in commercial services. However, the LPWA schemes sacrifice data rate to provide low-power and wide coverage features. Even if the communication link supports low data rate, it is necessary to investigate a novel networking that accommodates a huge number of LPWA clients distributed in very large geographic area. If the coverage area can be made movable in certain schedule, effective communication area of LPWA network can be easily expanded. Therefore, this paper proposes an application-oriented LPWA network with a moving gateway and geo-located stationary clients. The proposed network can reduce the total communication traffic in the network and shorten the total length of moving path by skipping to visit unnecessary clients. This network also can utilize the application-specific knowledge for traffic reduction and scheduling of the moving gateway. Based on the proposed network, we implemented a notification system for house-to-house trash collection using LoRa gateway and LoRa clients. Through some experimental measurements and discussions, we reveals the feasibility of the system deploying the proposed network.

Heterogeneous wireless systems such as a combination of mobile broadband wireless access (MBWA) and wireless local area network (WLAN) are candidates to attain higher throughput and wide coverage in the next generation mobile communication systems. A multimode receiver to demodulate signals with multiple air interfaces is required in the heterogeneous systems. In this paper, we discuss an implementation of frequency domain equalizer (FDE) in the multimode receiver on an application specific integrated circuit (ASIC). The proposed multimode FDE could realize adaptively demodulate two systems (single carrier and multi carrier) depending on propagation environment. A multimode FDE ASIC is designed and implemented on 180-nm complementary metal-oxide semiconductor (CMOS). Core size of multimode FDE chip is 17.6 mm2. The experimental results show that the ASIC yields a throughput of 48.1 Mbit/s at a sampling rate of 100 MHz. The results also show that the power penalty of the measured bit error rate (BER) performance is only 1 dB at a BER of 10-3in a 4-paths Rayleigh fading channel. We consider that the implemented ASIC is useful to demodulate signals with different air interfaces while optimally selecting an appropriate air interface in the heterogeneous wireless system.

This paper proposes an adaptive image compression algorithm suitable for highly-parallel software implementation. The proposed algorithm is based upon the block truncation coding (BTC), which is very simple but the image quality is not so good. In order to derive a better trade-off between reconstructed quality and computational complexity, an adaptive BTC algorithm coupled with the differential pulse code modulation (DPCM) is introduced. Furthermore, its highly-parallel data-driven scalable software implementation is discussed to realize an embedded multimedia communication system on a single chip for future various consumer appliances. Experimental evaluations of the proposed algorithm were performed using various benchmark images. The results illustrate that the proposed algorithm achieves over 3 dB better than the absolute moment BTC (AMBTC) with the same bit rate. In fact, evaluation result of the proposed data-driven implementation shows about 60 VGA images per second.

This paper presents an extended SIMD form data operation for multi-media signal processing and a performance evaluation of data-driven processor Qv-K1. By appending proposed data-parallel operation mechanism, the number of executed instructions is reduced compared to SIMD. The processing ability of this processor could be increased.

This paper describes the world's first commercial data-driven multimedia processors (DDMPs), developed jointly by Osaka University Kochi University of Technology, and Sharp Corporation. The data-driven principle underlying the structure of these processors was realized in a super-pipelined implementation, which was in turn based on a self-timed clocking scheme. This design made it possible to realize single chip DDMPs capable of executing tens of billions of signal processing operations per second with power consumption as low as 2 W. In terms of operations per watt, the processors exhibit threefold to tenfold improvement over conventional sequential digital signal processors (DSPs). The structure of this paper is as follows: 1) a brief introduction to the data-driven processing principle; 2) a detailed description of elementary modules for the realization of self-timed pipeline microprocessors; and 3) a description of the DDMP's developed thus far in the research project, which has continued for more than a decade. Also outlined here are the numerous advantages, in terms of both function and power consumption, of the self-timed pipeline over its synchronous counterparts. Commercially available DSP-oriented asynchronous data-driven processors and their practical applications to consumer appliances such as digital TV receivers are discussed; some programming examples are provided.

To realize a speech recognition system for daily usage, we need to consider the performance degradation due to the surrounding noise. If the surrounding noise is nonstationary, the conventional techniques, such as spectral subtraction or noise injection for templates, are not effective. A new method of speech parameter extraction in noisy environment is proposed as a font-end of a speech recognition system. This method applies a masking model to the observed signal before extracting the LPC parameters. Because the lower level noise components are masked by the speech, the degradation of the extracted parameters is reduced. According to experimental results for isolated word recognition, the improvement using the proposed method is about 4 dB in the SNR for white noise. The total improvement is over 25 dB when this method combined with a noise canceler using an adaptive digital filter.>