Demo Data from EDBT 2026 / reviewers in the wild / expert
Corneliu I. Toma
dblp:77/5779
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1975
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design › logic array
cellular logic array |
0.0 | 1 | 1975 | Cellular Logic Array for High-Speed Signed Binary Number Multiplication · IEEE Trans. Computers 1975 |
Integrated circuit design
digital arithmetic circuits |
0.0 | 1 | 1975 | Cellular Logic Array for High-Speed Signed Binary Number Multiplication · IEEE Trans. Computers 1975 |
Integrated circuit design › digital arithmetic circuits › integer multiplier
high-speed multiplier |
0.0 | 1 | 1975 | Cellular Logic Array for High-Speed Signed Binary Number Multiplication · IEEE Trans. Computers 1975 |
Integrated circuit design › digital arithmetic circuits
signed binary multiplication |
0.0 | 1 | 1975 | Cellular Logic Array for High-Speed Signed Binary Number Multiplication · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
simultaneous two-digit multiplication · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1975 | Cellular Logic Array for High-Speed Signed Binary Number MultiplicationabstractA new high-speed cellular logic array for multiplication of signed binary numbers is described. It uses a four-bit arithmetic logic unit MC10181 to achieve high speed and to reduce the number of interconnections. A multiplication algorithm which implements simultaneous multiplication by two digits of the multiplier results in a cellular logic array achieving high speed and involving less equipment. ment. A high-speed 4 X 2 multiplier chip is proposed. Corneliu I. Toma |
IEEE Trans. Computers | 1 |