Demo Data from EDBT 2026 / reviewers in the wild / expert
Ingrid Jansch
dblp:77/6708
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 50% Integrated circuit design · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
self-checking circuits |
0.0 | 1 | 1988 | Definition and Design of Strongly Language Disjoint Checkers · IEEE Trans. Computers 1988 |
Integrated circuit design › digital circuit design
sequential circuit design |
0.0 | 1 | 1988 | Definition and Design of Strongly Language Disjoint Checkers · IEEE Trans. Computers 1988 |
Methods — techniques the papers use, named apart from their topics
regular combinatorial self-checking components · 0.0formal definition · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | Definition and Design of Strongly Language Disjoint CheckersabstractStrongly language-disjoint (SLD) checkers are to sequential systems what strongly code-disjoint checkers are to combinatorial systems. SLD checkers are the largest class of checkers with which a functional system can achieve the totally self-checking goal. Self-checking sequential systems are first addressed, and formal definitions of SLD checkers are given. The design of SLD checkers based on regular combinatorial self-checking components is then considered.> Ingrid Jansch, Bernard Courtois |
IEEE Trans. Computers | 1 |