Brain-computer interfaces (BCIs) have made remarkable progress in recent years, driven by advances in neuroscience and clinical applications. For practical use, underlying processing systems must meet strict latency and power budgets. However, existing BCI systems typically rely on a single processing node to handle the entire workload, making it difficult to satisfy these budgets across diverse applications. In this work, we present TierX, the first simulation framework for design space exploration of multi-tier BCI systems. TierX models heterogeneous processing nodes across tiers, including implanted processors, body-attached devices, and external servers, together with diverse communication and powering methods. It navigates the extensive design space to identify optimal (1) workload partitioning options and (2) system configurations that leverage the strengths of each tier. We validate TierX on representative system configurations and demonstrate its effectiveness across diverse use cases.

Finding optimal solutions for Combinatorial Optimization (CO) problems is challenging. Compared to power-hungry cryogenic quantum computer and time-consuming classical computer, quantum-inspired Ising machine solves CO problems at room temperature with fast optimization speed, low power consumption, and low cost. Nevertheless, the Ising machine still faces several challenges: digital CMOS Ising machines increase interaction freedom at the cost of greater area and larger processing time; in analog Ising machine, oscillator spins find it hard to differentiate spin states without the assistance of the post-processing algorithm, and latch spins suffer from mismatches. To address these issues, we propose an oscillator-based 3-D CMOS Analog Ising Machine (CAIM) which adopts the 12-way toroidal Hexagonal Close Packed (HCP) structure, Supply-And-Bulk Injection Locking (SABIL), and dual-mode tunable coupler. The toroidal HCP structure exhibits >2 & times; interactions compared to conventional 3-D Ising machine, while SABIL and dual-mode tunable coupler settle oscillators to a bistable ground state 2.2 & times; quicker with an 8.5 & times; wider lock range (within 5 cycles). The proposed CAIM successfully solves 3-D max-cut problems and achieves a normalized Hamiltonian energy of more than 0.98 with a maximum perfect accuracy prevalence (PAP) of 91.67%. Measurement results on a sample random Max-Cut instance demonstrate that CAIM converges to within 1.7% of the reference optimum in 5 cycles.

Unmanned Aerial Vehicle (UAV)/drone vision and navigation require low-power 3D depth-sensing with robustness against strong/weak light and various weather conditions. CMOS image sensor (CIS) and light detection and ranging (LiDAR) can provide high-fidelity imaging. However, CIS lacks depth sensing and has difficulty in low light conditions. LiDAR suffers from heavy fog and is costly. Radar is resilient in poor weather but tends to be bulky and expensive. Ultrasound imaging system (UIS), on the other hand, is robust in various weather and light conditions and is cost-effective; however, it usually has low imaging resolution and low frame rate. Using a higher frequency ultrasound theoretically enables higher resolution, yet this comes at the cost of short range due to greater attenuation and severe grating lobe phenomenon. Compared to prior air-channeled ultrasound imaging systems, this work is first to integrate low-frequency (LF) and high-frequency (HF) dual band ultrasound imaging into SoC, achieving highest angular resolution so far with near-zero frequency switching latency and typical 11.04M focal point/s throughput to enable real-time high resolution 3D imaging. System level validation including signal-to-noise ratio (SNR) VS range characterization, hybrid LF–HF imaging, two-point separation demonstrating 0.5° angular resolution, and in-air measurements on a flying drone confirms reliable operation at a 7 m range and 21 frames per second (fps) for both LF and HF modes. These results establish the hybrid dual-band SoC as an effective and practical 3D depth-sensing solution for UAV navigation under challenging environmental conditions. The SoC is implemented in 180 nm 1P6M Standard CMOS, occupies 30mm${}^{\mathbf {2}}$and consumes 116.1 mW.

This article presents an energy-efficient 13-bit high-speed SAR-assisted cyclic ADC. The$1^{\text {st}}$stage 6-bit SAR ADC coarsely quantizes the input signal. The proposed charge-reused 2-bit/cycle cyclic ADC doubles the conversion speed with 50% reduction in capacitor number. Owing to the comparator noise suppression circuit and mismatch robustness of the cyclic ADC, an interstage gain of only$2\times $is required, which significantly relaxes the amplifier design and improves its total harmonic distortion (THD). Fabricated in 40nm 1P8M CMOS, the proposed SAR-assisted cyclic ADC achieves 13b resolution with SNDR and SFDR of 66.5dB and 80.1dB, respectively, with a Nyquist-rate input at 70MS/s without calibration while consuming 0.88mW power, yielding FoMSand FoMWof 175dB and 6.9fJ/conv., respectively. The ADC demonstrates a sub-1dB SNDR variation across the measured 9 chips, presenting the robustness against variations.

Capacitively-Coupled Instrumentation Amplifiers (CCIAs) are widely used as AC-coupled, low-noise amplifiers in many multi-channel, area-intensive sensor interface applications. However, the need for a trade-off between the front-end gain and CCIA area, imposed by the input capacitance, restricts the miniaturization of such sensors. We propose a Complementary Transimpedance Boosting (CTB) technique to relieve this challenging gain versus area trade-off. The proposed CTB applies to both the DC and AC paths of a CCIA. CTB also reduces AC gain degradation, suppressing low-side gain peaking of the frequency response without significantly increasing input-referred noise. The Gain-Noise-Area Efficiency (GNA) and Gain-Power-Area Efficiency (GPA) factors are also introduced for holistic comparisons with other front-end amplifiers regarding noise, gain, and power consumption. CTB-based CCIAs (CTB-CCIA) are fabricated in 0.18$\mu$m CMOS, with the highestsingle-stageAC gain of 289 V/V achieved. Occupying only 0.011 mm$^{2}$, a conventional CCIA with the same area will have 14.4$\times$less gain while requiring at least two stages. The CTB-CCIA has a competitive NEF of 4.92 within a signal bandwidth of 0.21 Hz – 8.7 kHz, suitable for multi-channel applications.

The wearability of emotion classifiers is a must if they are to significantly improve the social integration of patients suffering from neurological disorders. Such wearability requires the use of low-power hardware accelerators that would enable near real-time classification and extended periods of operations. In this paper, we architect, design, implement, and test a handcrafted, hardware Convolutional Neural Network, named BioCNN, optimized for EEG-based emotion detection and other similar bio-medical applications. The architecture of BioCNN is based on aggressive pipelining and hardware parallelism that maximizes resource re-use and minimizes memory footprint. The FEXD and DEAP datasets are used to test the BioCNN prototype that is implemented using the Digilent Atlys Board with a low-cost Spartan-6 FPGA. The experimental results show that BioCNN has a competitive energy efficiency of 11GOps/W, a throughput of 1.65GOps that is in line with the real-time specification of a wearable device, and a latency of less than 1ms, which is much smaller than the 150ms required for human interaction times. Its emotion inference accuracy is competitive with the top software-based emotion detectors.

This paper presents the design and modeling of an inductive wireless power transfer by utilizing printed spiral inductors on the surface of a medical hydrocolloid dressing. Hydrocolloid is a flexible and bio-compatible polymeric dressing that is medically used and approved. In this work, the dressings with planar dimensions of 10cm×10cm and thickness of less than 1mm are used as flexible substrates. The spiral inductors are modeled, and designed. The spirals are then screen printed using silver conductive paste and a 90um mesh size leading to a metallization thickness of ∼20um. Before printing, the water-resistant surface of the hydrocolloid is coated with Polyvinyl Acetate (PVA). A wireless power transfer link between the printed spirals on the hydrocolloid is experimentally tested and validated reaching a voltage link gain of around 40%.

Classification of EEG under wearable environment faces many challenges including motion artifact, electrode DC offset, noise and limited available energy source. This paper describes the design consideration of a multi-channel machine-learning based EEG classification and recording processors for wearable form-factor sensors. The goal is to optimize the detection performance while balancing the analog and digital signal processing to optimize its energy consumption. On-chip classification significantly helps achieving energy-efficiency by reducing the communication overhead of the data. With epileptic seizure detection and recording system examples, we start from choosing number of channels, the sampling rate, and how to effectively extract features out of the down-sampled data. After that, classification algorithms are also discussed in detail. When verified with the Children's Hospital Boston-Massachusetts Institute of Technology (CHB-MIT) EEG database, based on Repeated Random Sub-Sampling validation, the seizure detection sensitivity and specificity of the Non-Linear SVM are improved by 12.4%P and 3.56%P, respectively, compared to the Linear-SVM. The LSVM and NLSVM processors are fabricated in 0.18μm 1P6M CMOS and consume 1.52μJ/classification and 1.34μJ/classification, respectively. Finally, the on-chip memory requirements for storing the raw seizure data is discussed.

This paper presents the design of an area- and energy-efficient closed-loop machine learning-based patient-specific seizure onset and termination detection algorithm, and its on-chip hardware implementation. Application- and scenario-based tradeoffs are compared and reviewed for seizure detection and suppression algorithm and system which comprises electroencephalography (EEG) data acquisition, feature extraction, classification, and stimulation. Support vector machine achieves a good tradeoff among power, area, patient specificity, latency, and classification accuracy for long-term monitoring of patients with limited training seizure patterns. Design challenges of EEG data acquisition on a multichannel wearable environment for a patch-type sensor are also discussed in detail. Dual-detector architecture incorporates two area-efficient linear support vector machine classifiers along with a weight-and-average algorithm to target high sensitivity and good specificity at once. On-chip implementation issues for a patient-specific transcranial electrical stimulation are also discussed. The system design is verified using CHB-MIT EEG database [1] with a comprehensive measurement criteria which achieves high sensitivity and specificity of 95.1% and 96.2%, respectively, with a small latency of 1 s. It also achieves seizure onset and termination detection delay of 2.98 and 3.82 s, respectively, with seizure length estimation error of 4.07 s.

An interference and multipath resilient Body Channel Communication transceiver with ground effect cancellation for binaural hearing aids application is presented. The channel characteristics are measured between the intended points of transmission and reception to measure the path loss. The energy efficient transceiver is based on Hybrid OFDM folded in FSK modulated signal to mitigate the multipath problem in binaural hearing aids. By eliminating the needs for DACs, ADCs and power amplifier, the proposed design is free from peak-to-average power ratio (PAPR) problem. It utilizes 4 channels Adaptive Frequency Hopping technique for resisting interference. A variable gain LNA is exploited in this implementation to overcome the variable ground effect of BCC. The transceiver is implemented in 65nm CMOS process with an active area of 2.28mm2for baseband OFDM and a data rate transmission of 1 Mbps while consuming 1.54mW.

This paper describes the design and implementation of a fully integrated Tx/Rx front-end interface for Doppler Imaging with Piezoelectric Micromachined Ultrasonic Transducer (pMUT). The 4-Level Time Gain Compensation (QL-TGC) readout channel with an integrated biasing bank reduces Rx power with satisfactory noise performance (NF=17) and minimal area. The 65nm CMOS chip occupies 200 × 300 μm and has a total power consumption of 23μW, which is a 4x and 25x improvement over the state-of-art pMUT interface circuits, respectively.

This paper presents an 8-channel electroencephalograph (EEG) classification processor for seizure detection and recording. To integrate 8 channels, an area- and energy-efficient filter architecture using Distributed Quad-LUT (DQ-LUT) is proposed, which reduces area by 64.2% with minimal overhead in power-delay product. The on-chip patient specific classification with a Linear Support-Vector Machine (SVM) results in 82.7% seizure detection accuracy with a 2 second latency using the CHB-MIT EEG database [1]. The overall energy efficiency is measured as 1.52μJ/classification while operating at 8 channel mode.

This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both input sides of comparator, the MSB cycling step can be hidden by hold mode. Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced by 68% compared with conventional SAR ADC. Moreover, switching energy distribution is more uniform over entire output code compared with previous works.

A wearable electrocardiogram (ECG) acquisition system implemented with planar-fashionable circuit board (P-FCB)-based shirt is presented. The proposed system removes cumbersome wires from conventional Holter monitor system for convenience. Dry electrodes screen-printed directly on fabric enables long-term monitoring without skin irritation. The ECG monitoring shirt exploits a monitoring chip with a group of electrodes around the body, and both the electrodes and the interconnection are implemented using P-FCB to enhance wearability and to lower production cost. The characteristics of P-FCB electrode are shown, and the prototype hardware is implemented to successfully verify the proposed concept.

A 200 Mbps 0.02 nJ/b dual-mode inductive coupling transceiver is proposed for cm-range inductive coupling interconnection. The parallel capacitor combined with the TX inductor enhances the transmitted signal slew rate so that it increases the transmission distance by twofold. The proposed intersymbol interference (ISI) reduction scheme of the transmitter improves data rate up to 200 Mbps. And the proposed pulse generation scheme allows the transceiver to consume only 0.02 nJ/b energy. The transceiver consumes 0.012 mm2in a TSMC 0.25 um CMOS process.

An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 /spl mu/W at sub-1V. The DSP consumes only 10 /spl mu/W at 0.9-V single supply, and occupies 0.3 mm/sup 2/ with gate count of 10k using 0.18-/spl mu/m CMOS process.