Vehicular Ad Hoc Networks (VANETs) have received considerable attention in recent years. VANETs provide many services and applications such as Internet access Voice over Internet Protocol (VoIP) and information dissemination. Due to dynamic changes in the network topologies, various routing protocols have been studied in the vehicular environments. However, the communications between source and destination vehicles involve many intermediate vehicles, and due to the high mobility of vehicles, these communication links become disconnected. In this paper, we propose a distributed routing protocol in VANETs with the help of roadside units (RSUs). The proposed scheme includes vehicle registration, finding the location of destination vehicle and the handover maintenance. The simulation results show that our proposed protocol is suitable for vehicles communications in VANETs.

Following the trend of miniature intelligent sensing, wearing small, integrated wireless sensor nodes, such as one with accelerometers and compasses, to capture human body motions may have many applications in medical care and computer animation. In this paper, we demonstrate the use of intelligent sensors to capture human motions for home rehabilitation. We design a game to help a patient to conduct his/her rehabilitation program. For each exercise, the patient is instructed to wear sensors on specified movable body parts. The system will then estimate the quality of the movements and give scores as if it is advised by a therapist. In this way, patients will no longer feel painful and boring as that in traditional rehabilitation, which is typically done in hospitals.

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given.

We describe a new linear programming (LP)-based hierarchical pitchmatching method. With a simplified treatment of the intercell constraints, the size of the LP problems is significantly reduced as compared to the best known results. In particular, the pitchmatching problem is decomposed into independent subproblems by exploiting the layout slicing structure. Each subproblem is further "folded" to reduce the LP problem size. We prove that the new method generates smaller LP problem than the previously best known approach. Experimental data show that the LP problem size can be 10 times smaller.>

A common method of locating electrical shorts in VLSI layouts is to build a connectivity graph of the shorted net and then find the shortest path between the two offending signals. The memory requirement of this method is proportional to the size of the net, which can be quite large. This paper presents a dynamic graph construction algorithm that significantly reduces the peak memory requirement. The algorithmic framework allows continuous trade-offs between run times and memory requirements.>

We describe a new linear programming (LP)-based hierarchical pitchmatching method.Whh a simplified treatment of the intercell constraints, the size of the LP problems is significantly smaller than the best known methods.In particular, the pitchmatching problem is decomposed into independent subproblems by the natural slicing structure in layout.Each subproblem is folded further to reduce the LP problem size.Experiments show that the LP problem size can be 10 times smaller than the best known result.

In this paper we present an object oriented data model for VLSI/CAD data. A design data manager (DDB) based on such a model has been implemented under the UNIX/C++ environment. It has been used by a set of diverse VLSI/CAD applications of our organization. Benchmarks have shown it to perform better as compared to commercial object oriented database systems. In conjunction with the ease of data access, the data manger served to improve software productivity and a modular program architecture for our CAD system.

An algorithm that implicitly searches the flattened VLSI netlist data space without first constructing it is presented. In traditional methods, the entire search space of size n (e.g. the total number of instances) is constructed explicitly to allow a fast O(1) query time. The new algorithm uses circuit hierarchy to prune the search effectively. It is shown that the size of a hierarchical netlist is o(n), and a query can be executed in O(1) amortized time.>

Lo and Steiger resolved the complexity question for computing a planar ham-sandwich cut by giving an optimal linear-time algorithm. We show how to generalize the ideas to every fixed dimension d > 2 by describing an algorithm that computes a ham-sandwich cut in Rd in time O(nd–1–a(d)), for some a(d) > 0 (going to zero as d increases). For d = 3,4, the running time is almost proportional to ed–1(n;n/2), where dd(k;n) denotes the maximal number of k-sets over sets of n points in Rd, and with the current best bounds, we get O(n3/2 log2n/log n) running time for d = 3 and O(n8/3+e) for d=4. We also give a linear time algorithm for three dimensional ham-sandwich cuts when the three sets are suitably separated.

The authors describe a new variant of the segment tree approach for VLSI design rule checking. The best known algorithms to date for flat VLSI design rule checking require O(n log n) expected time and O( square root n) space, where n is the total number of edges on a mask layer of the chip. The expectation is with respect to a uniform distribution of edges over the chip area. The authors present a new algorithm of O(n log m) expected time complexity, where m is the maximum feature size for a given mask layer. Since m is bounded by the height of a chip, i.e. m=O( square root n), the new algorithm is adaptively more efficient than O(n log n). For layers such as diffusion or contact windows where m is independent of the chip size, i.e. m=O(1), the new algorithm runs in O(n) expected time, a definite improvement. The improved time efficiency is achieved without sacrificing O( square root n) space complexity.>

Article On minimal closure constraint generation for symbolic cell assembly Share on Authors: Debaprosad Dutt AT&T Bell Laboratories, 1247 South Cedar Crest Blvd., Allentown, PA AT&T Bell Laboratories, 1247 South Cedar Crest Blvd., Allentown, PAView Profile , Chi-Yuan Lo AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 736–739https://doi.org/10.1145/127601.127761Online:01 June 1991Publication History 6citation150DownloadsMetricsTotal Citations6Total Downloads150Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper, we bound the complexity of the major algorithms of 1-d compaction in graph solution and module assembly to be Ο(n15logn). An 1-d hierarchical module assembly method is shown to be free from the x-y interlock problem and achieves significant improvement in space and time requirements by exploiting hierarchy.

A hierarchical search software package that allows an application to retrieve flattened netlist data from a hierarchical netlist database. An algorithm is presented that implicitly searches the entire VLSI CAD net list data space without first constructing it. While traditional methods construct the entire search space explicitly, which helps to achieve a fast O(1) query time but requires Omega (n) space, this method relies on the circuit hierarchy to prune the search effectively. It is shown that the hierarchical net list data space is smaller by a factor of O(n/sup epsilon /). Where O>

This paper describes a new variant of the segment tree approach for VLSI design rule checking. The best known algorithms to date for flat VLSI design rule checking require O(nlogn) expected time and O(√n) expected space, where n is the total number of edges on a mask layer of the chip. We present a new algorithm that can run in O(nlogm) expected time, where m is the maximum feature size on a particular mask layer. Since the maximum feature size must be bounded by the height of a chip, i.e. m ≤ O(√n), the new algorithm is adaptively more efficient than O(nlogn). For layers such as diffusion or contact windows where the maximum feature size is independent of chip size, i.e. m = O(1), the new algorithm runs in O(n) expected time, a definite improvement. The improved time efficiency is achieved without sacrificing O(√n) expected space complexity.

This paper describes a new algorithm that automatically generates tub regions for VLSI symbolic layouts with quality comparable to that of human designers. The algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. In addition, the algorithm runs at O(n/sup 2/) time and O(n) space with the expected run time of O(n log n).

We present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. In particular, we propose a new hierarchical method for fast and optimal placement of the transistors in a cell. The method minimizes the number of diffusion breaks, and allows a further pursuit of a secondary optimization objective, such as routing channel density. For cells with non-uniform transistor widths, the transistors are folded in such a way as to optimize a cost function which is a good approximation to the area of the final(compacted) layout of the cell. We also analyze the characteristic nature of routing in cell generation problem, and design an algorithm for doing routing over the transistors; such routing reduces the routing channel density in the central region of the cell. The routing in the central region is completed by a new channel router at, or near, the channel density. The algorithms are implemented in a system call GENAC. The input to GENAC is a transistor net list, describing the connectivity as well as the size and type of each transistor. The output is a synthesized layout of the cell in symbolic language.

A new heuristic two-dimensional symbolic layout-compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce the layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bounded by Ο(T1), where T1 is the run time of a typical one-dimensional compactor.

A design data manager is emerging as an important component of an integrated CAD system. The authors present a semantic data model and an architecture for VLSI/CAD databases. The data model provides mechanisms to represent the design entities the relationships among them in a unified way. A key feature of the system architecture is that it exploits design hierarchy to provide high performance. A data manager based on this model has been implemented and used by a set of diverse applications. In conjunction with efficient data flow, the data manager can serve to improve software productivity.>

New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. The scanline algorithm virtually eliminates the redundant computation present in similar systems. It solves the VLSI layout analysis problem in O(n+k) expected time and O( square root n) expected space, where n is the total number of input segments and k is the total number of intersection points. The new scanline algorithm is robust in what it will maintain its performance over a wide range of layout styles. Experimental results show that the running time is O(n/sup 1.0547/), i.e. that these algorithms enable one to perform VLSI layout analysis in nearly linear time.>

In this paper, we will present algorithms developed for an advanced fault simulation system in the MOTIS simulation environment. In particular, the algorithm to perform fault modeling and collapsing is first reviewed. Efficient algorithms to perform fault simulation are discussed in terms of fault list manipulation and primitive evaluation. The simulator realizes a speed gain factor of 787 to 2088 over serial fault simulation. Special emphasis is on an innovative fast unit delay fault simulation algorithm that achieves an additional 33-39-percent improvement in speed and 20-28-percent improvement in memory usage.

This paper describes a fault simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. The simulator provides the capability of modeling and simulating both the classical input/output stuck-at faults and the non-classical transistor stuck-on and stuck-open faults.