In this paper, we propose an ultra-low power current comparator suitable for low-frequency to medium- frequency applications with a stringent power budget. The circuit uses diode-connected transistors and feedback judicially to reduce the power dissipation significantly with a minimal increase in delay. As a result, the overall power-delay product (i.e., figure of merit - FoM) of the proposed current comparator is better than that in existing current comparators. For a fair comparison, the proposed and existing designs are simulated in TSMC 180 nm technology with 1.8 V supply voltage. The power dissipation of the proposed comparator is 168$n$W at 1 MHz signal frequency with 100$n$A signal amplitude. As a result, the FoM of the proposed comparator is 2.78 fW-sec which is at least 2.8 times improved compared to the better existing comparator available in the literature.

Switched capacitor common-mode feedback (SC-CMFB) is a popular technique for stabilization of the output common-mode level of fully differential operational amplifiers. It provides advantages of excellent linearity across a wide amplifier output swing, lowest power consumption, and better feedback loop stability in contrast to continuous CMFB; and hence, are suitable for realization of high-gain wide-swing low-power opamps. But, its implementation demands careful consideration of some practical aspects, a number of which are well documented in literature. However, its detrimental effect on the amplifier's differential-mode gain is not quite explored. Equivalent resistive loading from the SC-CMFB is the reason for this effect, and is particularly important in op-amps meant to have large gain (like, the folded cascode). This SC-CMFB induced drop in amplifier dc-gain, and the consequent effect on the design of continuous and discrete-time integrators have been discussed together with pertinent analytical derivations and transistor level simulations. A few practical guidelines and circuit topologies for minimizing the gain reduction effect have also been provided.

This paper presents a current-mode triline ternarylevel coded differential signaling scheme for high-speed data transmission across on-chip global interconnects. An energy efficient current-mode triline transceiver pair suitable for this signaling scheme has been proposed. Compared with a voltage mode receiver with resistive termination, the proposed active terminated current-mode receiver reduces the signal current by 7.8 times and the signaling power by 2.6 times. Two data transmission schemes are proposed for using this transceiver pair. In the first scheme, two data streams are directly transmitted over the three lines link, thereby having a wire efficiency of 67%. In the second scheme, five data streams at half rate are encoded and serialized to send over the three lines, thereby having a wire efficiency of 83%. A prototype design has been implemented in a UMC 0.18-μm technology for an interconnect of length 5 mm. The measured energy efficiency of the triline transceiver in a direct transmission scheme for the data rate of 7.4 Gb/s is 0.61 pJ/bit. With the encoding scheme, the energy efficiency is 1.24 pJ/bit for a total data transmission of 9.25 Gb/s.

Here, we propose high performance buck converter architecture suitable for embedded applications. The proposed converter has high power efficiency, high power density, good driving capability, low output ripple, and good line and load regulation. The step down converter is constructed using a simple building block called cross coupled converter. As this block use low swing internal signals to control half of its switches, the required switching loss decreases and these internal control signals enable us to use thin oxide transistor for making switch smaller and reducing power further. In addition, converter uses all the good features of non-overlapping rotational interleaving switching scheme. Switching frequency of the converter is dynamically adjusted based on load current to maintain high power efficiency. Good transient performance is achieved by using dynamic leaker circuit with a marginal increase of static current. The converter is designed in 0.18- m CMOS process to get regulated 1.3-1.6 V output from 3.3 V input supply while output ripple is below 42 mV and provides 86% peak power. For 75% power efficiency, power density of the converter is 0.43 W/mm2using total 490 pF capacitor.

A knowledge based approach empowered by geometric programming (GP) for analog circuit synthesis and sizing is presented. Analog circuit performance specification is mapped to various building blocks of a circuit topology. Thereafter the topology is modified according to the design rules in the library. Each modification is validated over two steps. In the first step, dc performances constraints are introduced. If qualified, ac performance constraints are introduced. Validation over two steps helps to gradually close in on input specifications removing any undesired correction made initially, resulting in faster convergence.

This paper presents a method for optimal sizing of CMOS low drop out regulator circuits. The technique relies on the observation that many of the performance metrics of a LDO regulator can be approximated as posynomial functions of design variables. This allows the design problem to be cast as a geometric program. Geometric program is particularly attractive as the tool for optimization as --1)it can be solved very efficiently, 2)it always finds the global minima, 3)infeasible specifications are readily determined and 4)the final solution is completely independent of the initial guess. As a result CMOS LDOs may be conveniently synthesized; moreover the optimal trade off curves between the competing performance metrics, can be obtained very fast.

This paper presents a non overlapped rotational time interleaving scheme to eliminate shoot-through current in switched capacitor dc-dc converters. In addition to the improvement of power efficiency this scheme also reduces the output voltage ripple. In the integrated converter, current regulation control is incorporated with the basic switched capacitor converter to get the output voltage at a pre-specified level. The proposed converter has been designed in 0.18μm CMOS process with a total flying capacitance of 330pF and load capacitance of 50pF. The capacitors are chosen such that on-chip implementation is possible. The basic switched capacitor converter provides 3.3V to 1.45V conversion and achieves power efficiency of 80.7% and output voltage ripple of 5.7mV at 10mA output current. For the same output current the integrated converter achieves a power power efficiency of 73.5% and output voltage ripple of 5mV for 1.35V output voltage.

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as posynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converge to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation.

An analytical-knowledge-based statistical method is developed to derive macromodels for the highly nonlinear AC response functions of CMOS op-amp circuits. Simple circuit analysis is used to motivate the use of logarithmic transformations. By this transformation, linear models are fitted over a large domain of the independent variables (typically, transistor widths) with very few circuit simulations. From circuit analysis it is deduced that poles and zeroes are appropriate for empirical modeling instead of directly modeling the response functions like unity gain frequency or phase margin. We have demonstrated the usefulness of the proposed method by using it to model the transfer function of a two-stage compensated CMOS op-amp circuit. The model is compared with SPICE3 simulations and shown to have excellent predictive capability, with a speed-up of more than 500.