This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.

This article presents a 25 Gb/s pulse amplitude modulation 4-level (PAM-4) receiver that has only two comparators per data path for low power design. The receiver includes a pulse amplitude comparator that detects the amplitude difference in the differential input signal and compares it with the difference in the reference voltage. A continuous-time linear equalizer and decision feedback equalizer (DFE) are used to compensate for the channel loss and mitigate the inter-symbol interference. A modified summation method is introduced in the DFE to accommodate the reduced number of feedback signals owing to the decreased number of comparators. The proposed receiver is fabricated by a 28 nm CMOS process. At a supply voltage of 1 V and data rate of 25 Gb/s, the total power consumption is measured to be 10.298 mW. This results in an energy efficiency of 0.41 pJ/b. This represents an approximately 13% improvement compared with the PAM-4 receiver with the conventional structure.

This paper presents a digital clock and data recovery (CDR) designed for a faster approach to its steady-state and prevention of harmonic locking. By adopting a two-stage frequency detection system, the proposed CDR ensures a rapid and robust harmonic-lock-free frequency acquisition. The circuit is implemented and fabricated in a 28 nm CMOS process using a 1.0 V supply. The active area occupies 0.12 mm2. It covers from 1.62 to 8.1 Gb/s, making it adaptable to embedded DisplayPort (eDP) interfaces. The prototype achieves the rms jitter and the peak-to-peak jitter is 5.54 psrmsand 27.53 psppat 8.1 Gb/s, respectively. Its lock time is reduced within 2 μs for +170% frequency error.

This paper presents a transmitter with quadrature clock corrector (QCC) and phase controller for reducing EMI problem. The phase controller consists of phase interpolator and transmission gate (TG). The transmission gate is added to turn function on and off. The quadrature clock corrector is used for signal integrity. The circuit is designed in 180-nm CMOS process using 1.8-V supply. The operating frequency is 3.2 Gbps. For duty cycle distortion of 30% ~ 70% and phase error of ±30 degrees, the maximum duty cycle error of corrected clock is about 0.4%, and the phase error between the OUT0 and OUT90 signal is up to about 3.9 degrees. The duty correction time is about 5ns and phase correction time is about 36ns. And the maximum current peak of output drivers is 23% less than that of conventional transmitter.

A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 μm CMOS process and contains 0.95 M gates.

An adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing filter is based on Miller's theorem and composed of metal-insulator-metal capacitors and a sub-amplifier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satisfies the specification of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 and 0.5 UI for 5 and 8 m cables, respec- tively. The core area is 286 × 380 μm2and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.

This paper presents a 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme which has no phase noise degradation. The controllable loop filter enables the CDR circuit to change the operation mode without the output phase noise degradation and the stability problem. The modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13 μm CMOS technology. The RMS jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with off-chip drivers at 5.4 Gb/s data rate.

This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic (MSFSL) is proposed in this paper which achieves low power and small area. In 0.13μm CMOS process, TSGRO-TDC has a 3ps raw resolution and first-order noise shaping.

In this paper, a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link is presented. The process variation compensator not only reduces the error of spread ratio but also guarantees the reliability of the operation of an SSCG against process variation. The proposed SSCG has been implemented in 0.18-mum CMOS process and supports 10-phase 270 MHz and 162 MHz output clock. The experimental results show that the average rms jitter of 270 MHz output clock is 4.7 ps without spread spectrum clocking. 8.75 dBm of the peak reduction and 5000 ppm of spread ratio with the process variation compensator are achieved.