Information security in FPGAs is at risk; during system operation, data and usage patterns can potentially get imprinted into a chip's physical characteristics, allowing an attacker to later recover intellectual property or cryptographic secrets. Can “data burn-in” vulnerabilities in FPGAs be characterized at low cost? Specifically, can slight shifts in path delays due to burn-in be measured with enough precision? This paper contributes methods for self-characterization of delay changes using novel isolation of key FPGA transistors, improved clock sweeping, and enhanced estimation from launch-andcapture data. Hardware experiments on 2048 Xilinx Kintex-7 paths demonstrate measurement precision of 30-60 femtoseconds, which is more than 10× finer than previous self-characterization results. Further, results show that unintentional burn-in of FPGA LUT contents does indeed occur and can in some cases be detected within a single week, highlighting the need to deploy countermeasures.

Historically, space-based processing systems have lagged behind their terrestrial counterparts by several processor generations due, in part, to the cost and complexity of implementing radiation-hardened processor designs. Efforts such as NASA's SpaceCube seek to change this paradigm, using higher performance commercial hardware wherever possible. This has the potential to revolutionize onboard data processing, but it cannot happen unless the soft error reliability can be characterized and deemed sufficient. A variety of fault injection techniques are used to evaluate system reliability, most commonly fault emulation, fault simulation, laser testing, and particle beam testing. Combining multiple techniques is more complex and less common. In this study we characterize a real-world application that leverages a radiation-hardening by software (RHBSW) solution for the SpaceCube platform, using two fault injection strategies: laser testing and fault emulation. We describe several valuable lessons learned, and show how both validation techniques can be combined to greater effect.

Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to FPGA-based systems and presents a solution approach. Novel measurements of transients on 28nm FPGAs show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented; its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks.

Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip.

Electronic systems increasingly suffer from component variation, thermal hotspots, uneven wearout, and other subtle physical phenomena. Systems based on FPGAs have unique opportunities for adapting to such effects. Required, however, is a low-cost, fine-grained method for sensing physical parameters. This paper presents an approach to on-line sensing that includes a compact multi-use sensor implemented in reconfigurable logic, methods for instrumenting an application, and enhanced measurement procedures. The sensor utilizes a highly-efficient counter and improved ring oscillator, and requires just 8 LUTs. We describe how to measure variations in delay, static power, dynamic power, and temperature. We demonstrate the proposed approach with an experimental system based on a Virtex-5. The system is instrumented with over 100 sensors with a total overhead of only 1.3%. Results from thermally-controlled experiments provide some surprising insights and illustrate the power of the approach. On-line sensing can help open the door to physically-adaptive computing, including fine-grained power, reliability, and health management schemes for FPGA-based systems.

Random physical variations and noise are growing challenges for advanced electronic systems. Field programmable systems can, in principle, adapt to these phenomena, but two main problems must be addressed: how to efficiently characterize random variations and how to perform subsequent optimization. This paper addresses both of these questions. First, an approach to self-test is presented that uses on-chip noise emulation to quickly characterize some of the hidden variations in latches. Our noise-injection experiments demonstrate that there can be significant spreads in latch reliability even with current 65nm field-programmable gate arrays (FPGAs). We detected coefficients of variation as high as 77%. Second, we propose an approach to self-optimization using local resource swapping. Experiments on two FPGAs show improvements in mean-time-between-failures (MTBF) of up to 60%.

The amount of physical variation among electronic components on a die is increasing rapidly. There is a need for a better understanding of variations in transient fault susceptibility, and for methods of on-line adaptation to such variations. We address three key research questions in this area. First, we investigate accelerated characterization of individual latch susceptibilities. We find that on the order of 10 upsets per latch must be observed for variations to be adequately characterized. Second, we propose a method of on-line hardware reconfiguration using incremental place-and-route on FPGAs. Surprisingly, we find that highly localized place-and-route changes (e.g. restricted to groups of 8 flip-flops) are sufficient for realizing most of the possible benefits. Lastly, we quantify potential improvements in system-level soft error rates via Monte Carlo simulation experiments. The study highlights both what is required for and what can be gained by on-line adaptation.