FPGA technology mapping is an extensively studied problem. There is functional decomposition as well as graph covering-based approaches. For efficiency consideration, most existing algorithms are graph covering-based. However, logic synthesis can affect the graph covering results significantly. In this article, we propose an FPGA mapping algorithm with gate decomposition. Bin-packing is used to generate gate decompositions during mapping to avoid the decomposition choice pregeneration problem in existing approaches. Our results show that our algorithm can get an average of 13% area reduction over the state-of-the-art lossless synthesis-based mapping algorithm in ABC. When compared with industrial tool Vivado, we can get a significant area reduction of 35% on average.

In the post-Moore’s Law era, multi-chip and chiplet designs have become important trends. However, due to the limited inter-chip routing resources and large delays, partition a design into such multi-chips may lead to performance degradation. Existing netlist-based partitioning algorithms mostly targeting for cut size minimization do not handle performance well. In this article, we propose an Integer Linear Programming (ILP)-based algorithmic-level design partitioning algorithm for latency minimization. Our ILP formulation considers both partition resource constraints and inter-chip routing resource constraints. Multi-cycle communication is considered to address large inter-chip delay, together with local cache design for inter-chip data transmission bandwidth. For 2.5D FPGAs, our approach can improve the final clock frequency by 74.3% and circuit runtime by 60.2% when compared to Vivado. For multi-FPGA systems, we achieve 5 to 29 times higher clock frequency and an average of 11 times better performance over Synopsys HAPS software.

Most existing technology mapping algorithms use graph covering approaches and suffer from the netlist structural bias problem. Chen and Cong proposed a simultaneous simple gate decomposition with technology mapping algorithm that encodes many gate decomposition choices into the netlist. However, their algorithm suffers from the long runtime problem due to a large set of choices. Later on, A. Mishchenko et al. proposed a mapping algorithm based on choice generation with the so-called lossless synthesis. Nevertheless, their algorithm cannot guarantee to find and keep all good choices a priori before mapping. In this paper, we propose a simultaneous mapping with gate decomposition algorithm named AGDMap. Our algorithm uses cut-enumeration based engine. Bin packing algorithm is used for simple gate decomposition during cut enumeration. Input sharing based cut cost computation is used during iterative cut selection for logic duplication reduction. Based on a set of EPFL benchmark suite and HLS generated designs, our algorithm produces results with significant area improvement. Compared with the lossless synthesis algorithm, for area optimization, our average improvement is 12.4%. For delay optimization, we get results with similar delay and 9.2% area reduction.