This article presents a 1:4 single-ended binary-tree demultiplexer. The entire design, including true single-phase clock (TSPC) flip-flops, latches, and frequency divider, is composed of gated inverter blocks. The causes of voltage dip formation in flip-flops are analyzed and effectively eliminated. The setup time, hold time, and delay criteria of individual components are investigated and optimized over a variety of back-gate bias schemes as well as different supply voltages. Finally, a timing constraint is derived for the top-level demultiplexer architecture. The demultiplexer operates across a wide range of inputs from 1.6 to 60 Gb/s providing a selection of potential supply voltages ranging from 0.6 to 1.2 V. The chip’s power dissipation is mainly due to the dynamic power of the switching inverters and is self-adjustable on the basis of the input data rate. The circuit is designed and fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology with a chip area of 0.033mm2.

Even when following a well-structured top-down design methodology, system designers regularly face obstacles and pitfalls posed by speed/accuracy tradeoffs in modeling and simulation of complex hardware and software systems. Across the abstraction levels, modeling details grow exponentially, while simulation speed decreases by multiple orders of magnitude. To quantify these effects, we systematically generate, simulate, and evaluate grid-based systems-on-chip in a top-down open-source based tool flow. We map two parallel software applications onto a scalable grid of RISC-V processors and successively refine and validate the models at lower abstraction levels, namely TLM, ISS, RTL, and FPGA. Our comprehensive experimental evaluation over five abstraction levels quantifies the speed-accuracy tradeoffs in simulator build and run times. In addition to its educational value, our work can guide the system designer on an efficient path to a cycle-accurate software simulation on fully constructed hardware.

This paper presents system level design and measurements of a novel 2. 4GHz low-power and low-data-rate receiver, which uses Barker-coded Binary Phase-shift keying (BPSK) along with Pulse Position Modulation (PPM) as a communication scheme. To achieve low-power dissipation levels, direct-detection receiver architecture is used in combination with a 13-bits Barker Code Surface Acoustic Wave (SAW) correlator to improve co-channel interference. Furthermore, in order to improve receiver sensitivity, the baseband bandwidth is reduced by means of an innovative Narrowband Correlator (NBC), which allows for scalable receiver sensitivity versus data-rate. The receiver can be used as a Wake-up Receiver (WuRx) in Wireless Sensor Networks (WSNs) to minimize the power dissipation and provide asynchronous and on-demand data communication. The receiver is designed using TSMC65n technology and achieves a power dissipation of 142 $\mu$W from 1. 2V supply source and sensitivity of −44 and −50dBm at a data-rate of 2Mbps and 600 kbps respectively.

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling.

This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding 60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375 mW.

In this paper we propose a novel low-power receiver architecture which uses a direct-detection receiver in combination with a 2.44 GHz 13 bit Barker Code SAW correlator for improvement of co-channel interference. Furthermore, to improve receiver sensitivity, a narrowband baseband correlator which uses pulse position modulation (PPM) is proposed. The receiver can be used as a Wake-up Receiver (WuRx) in Wireless Sensor Networks (WSN) to minimize the power dissipation and provide asynchronous and on-demand data communication. We present a rigorous analysis of the receiver. It shows that the RF front-end (SAW correlator and envelope detector) alone suffers from poor sensitivity due to the high baseband bandwidth and the absence of an RF low noise amplifier. However, by adding the narrowband correlator with an innovative Pulse Position Modulation (PPM) scheme, the overall sensitivity of the receiver reaches -63.1 dB with an improvement of 17.7 dB due to the use of the narrowband correlator that reduces the baseband bandwidth from 50 to 0.84 MHz. By scaling the narrowband correlator bandwidth further down, the receiver sensitivity can be further improved.

We present a complete Visible Light Communication (VLC) system for experimental Vehicular VLC (V-VLC) research activities. Visible light is becoming an important technology complementing existing Radio Frequency (RF) technologies such as Cellular V2X (C-V2X) and Dedicated Short Range Communication (DSRC). In this scope, first works helped introducing new simulation models to explore V-VLC capabilities, technologies, and algorithms. Yet, experimental prototypes are still in an early phase. We aim bridging this gap with our system, which integrates a custom-made driver hardware, commercial vehicle light modules, and an Open Source signal processing implementation in GNU Radio, which explicitly offers rapid prototyping. Our system supports OFDM with a variety of Modulation and Coding Schemes (MCS) and is compliant to IEEE 802.11; this is in line with the upcoming IEEE 802.11 LC standard as well. In an extensive series of experiments, we assessed the communication performance by looking at realistic inter vehicle distances. Our results clearly show that our system supports even higher order MCS with very low error rates over long distances.

Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.

Two half-wavelength 122 GHz patch antennas were designed and manufactured by using Benzocyclobutene (BCB) as a dielectric layer above the SiGe BiCMOS wafer. It enables the full integration of the millimeter-wave transceiver circuits and the antennas on a single chip to simplify the packaging procedure at millimeter-wave frequencies, thereby reducing the cost. The two patch antennas are fed by different feeding methods, i.e. microstrip transmission line direct feed and proximity-coupled feed. They exhibit similar performance and offer the flexibility of designing the interconnects (feed lines routing) between the circuits and the antennas within the very limited chip area. The measured gain is 3.4 dBi at 122.5 GHz (the center frequency of the ISM band of 122-123 GHz) for both designs with a simulated efficiency of about 50%.

In this paper, a novel fully digital modulator for a switch mode power amplifier (SMPA) is presented. The modulator converts the input baseband amplitude and phase signals into a two-level pulse train for driving an RF SMPA. The simulation results demonstrated a proof of the concept. The proposed architecture is analyzed in terms of accuracy by measuring EVM. The impact of the modulator parameters on the SMPA performance is investigated and corresponding results are shown. The modulator was simulated with a 20 MHz LTE signal.

This paper presents the developed 60-GHz OFDM hardware demonstrators and the newly designed 60-GHz system architecture targeting for multi-gigabit wireless LAN applications. The hardware demonstrators developed so far are made up of maximum 1-Gbps OFDM baseband realized on FPGA platform and 60-GHz super-heterodyne transceivers fabricated by SiGe BiCMOS technologies. Wireless transmission in 60-GHz links is successfully demonstrated in indoor office environments. The next generation 60-GHz OFDM systems are designed to provide data rate higher than 3-Gbps utilizing the channel bandwidth of 2.16-GHz. Advanced channel coding schemes including low-density-parity-check (LDPC) coding are applied to have higher coding gain. RF transceivers are based on sliding IF architecture and designed to be compatible to the channel plans defined in the 60-GHz standards.

A fully integrated CMOS voltage-controlled oscillator (VCO) with very low phase noise is presented in this paper. Two filters were employed at top and bottom of the VCO core to maximize the voltage swing and to suppress flicker noise up-conversion. The measured phase noise at 1 MHz offset from a 9.3 GHz carrier is better than -126 dBc/Hz. And the phase noise variation over the whole tuning range (8.8 to 9.4 GHz) is as small as 3 dB. The VCO core consumes 32 mW from a 4.5 V supply. To the authors' knowledge, this is the lowest phase noise at 1 MHz offset for a silicon-based fully integrated VCO in this frequency range. The excellent phase noise performance makes the VCO especially suited for satellite communications.

This paper describes a millimetre-wave receiver beamforming for interference mitigation as well as array gain enhancement. Like the beamforming architecture in the IEEE 802.15.3c standard, it is based on only one baseband processor to support multiple N-element antenna arrays for low-cost implementation. This makes it difficult to estimate received signals and channel state information on each antenna, which restricts baseband digital processing and introduces large overheads for adaptive beamforming. For these reasons, the IEEE 802.15.3c standard utilizes 2-bit beam codebook for repetitive beam-searching, however it cannot offer adaptive interference nulling capability. We propose an algorithm to get received signal information on each antenna so that we can find optimum weight vectors for maximum beamforming gain. This also enables to mitigate co-channel interference, which increase total throughput by enhancing spatial re-use in multiple 60-GHz indoor networks. The structural difference from the IEEE 802.15.3c beamformer is to employ a continuous phase-shifter, however our implementation proves that it exhibits almost same-level complexity as 2-bit phase-shifters.

We present 60 GHz OFDM hardware demonstrators developed so far and outline design considerations for future developments. OFDM schemes have been developed to combat multi-path interferences in indoor wireless environments and further optimized for multi-gigabit data transmission in 60 GHz-band. RF and IF analogues front-ends (AFEs) have been developed with high-speed SiGe BiCMOS technologies. Future developments on AFE are mainly devoted to one-chip integration of RF and IF components based on a sliding IF architecture. We have already achieved wireless transmission of about 1 Gbps in an OFDM demonstrator, which will be continuously upgraded and optimized for higher data transmission with better link adaptability.

This paper describes a pragmatic approach on the up-conversion of WiMedia compliant UWB signals into the 60 GHz band. This dual band concept is based on propagation measurements at {3.1-10.6} and 60 GHz. Due to stringent frequency regulation, UWB systems operating in the 3.1 to 10.6 GHz bands are both bandwidth limited and power limited. Therefore, many potential users hesitate to deploy this technology. Up-conversion to the 60 GHz band and enhanced baseband parameters can make UWB technology more reliable and hence, more attractive. An experimental system based on a commercially available UWB development kit and IHPpsilas 60 GHz chip-set has been developed. The system architecture is described. Measurement results indicate that this combination may be interesting for many applications.

This paper reports implementation details of a 60 GHz short range communication system for data rates up to 2 Gbit/s. Based on a MATLAB model the main PHY parameters were derived, and the modules of the analog frontend were specified. For system verification, a demonstrator was developed. The analog RF and IF circuits of the demonstrator are implemented in a 0.25 μm SiGe BiCMOS technology. Measurement results of the analog modules and the complete demonstrator are given. Using OFDM modulation, the maximum data rate transmitted via airlink so far, is 960 Mbit/s.