Signal processing and multimedia applications are commonly modeled using Static/Cyclo-Static Dataflow (SDF/CSDF) models. SDF/CSDF explicitly specifies how much data is produced and consumed per firing during computation. This results in strong compile-time analyzability of many useful execution properties such as deadlock absence, channel boundedness, and throughput. However, SDF/CSDF is limited in its ability to capture how data is accessed in time. Hence, using these models often leads to implementations that are sub-optimal (i.e., use more resources than necessary) or even incorrect (i.e., use insufficient resources). In this work, we advance a new model called Static Dataflow with Access Patterns (SDF-AP) that captures the timing of data accesses (for both production and consumption). This paper formalizes the semantics of SDF-AP, defines key properties governing model execution, and discusses algorithms to check these properties under correctness and resource constraints. Results are presented to evaluate these analysis algorithms on practical applications modeled by SDF-AP.

FPGA devices provide flexible, fast, and low-cost prototyping and production solutions for system design. However, as the design complexity continues to rise, the design and synthesis iterations become a labor intensive and time consuming ordeal. Consequently, it becomes imperative to raise the level of abstraction for FPGA designs, while providing insight into performance metrics early in the design process. In particular, an important design time problem is to determine the maximum clock frequency that a circuit can achieve on a specific FPGA target before full synthesis and implementation. This early quantification can greatly help evaluate key design characteristics without reverting to tedious runs of the full implementation flow. In this work, we focus on the predictability of timing delay of circuits composed of high-level blocks on an FPGA. We are well aware of difficulties in tackling uncertainties in early timing estimation, e.g., an inherent gap between a high-level representation and gates/wires; extremely difficult delay estimation due to the randomness in physical design tools, etc. We show that the estimation uncertainties can be mitigated through a carefully characterized timing database of primitive building blocks and refined timing analysis models. We primarily focus on applications composed of data-intensive word-level arithmetic computations from the DSP domain and specified using static dataflow models. Our experiments indicate that for these applications, timing estimates can be obtained reliably within a good error margin on average and in the worst case. As future work, we plan to fine tune the timing database by modeling resource utilization effects and inter-primitive/actor routing delay via variants of Rent's rule and related efforts. We are also interested in exploring dynamic sub-cycle timing characterization.

In this paper we present a graphical programming environment for hardware designs targeted at FPGA devices. We first introduce LabVIEW™, a scientific software system, and its modular virtual instrumentation programming paradigm. Then, we discuss how LabVIEW FPGA enables application domain experts without prior knowledge of hardware description languages (HDLs) to program reconfigurable hardware devices. Initially many LabVIEW FPGA users were high-level (software centric) application domain experts in the area of control with prior knowledge of LabVIEW, where they benefited from a new fast and reliable target, namely FPGAs. Recently, we have found that system level integrators with lower level hardware design interest, but still no working experience in detailed HDL coding, have been able to use LabVIEW FPGA to successfully implement high-speed hardware designs. Here we focus on how LabVIEW facilitates reconfigurable hardware designs for applications of ultra-high speed control, complex timing and synchronization, hardware-in-the-loop (HIL) testing, etc. Specifically, we detail its modeling, simulation, and debugging capabilities as well as its rigorous semantics as a programming and deployment framework. Furthermore, we use application use cases to illustrate how LabVIEW FPGA can support a flexible, reliable and cost-effective hardware design.