Since the problem of power integrity has become a critical issue that limits design performance, obtaining the supply current waveforms at early design stages is essential to achieve efficient reduction of supply noise. Therefore, a high-level current macro model is proposed by Bodapati and Najm for logic blocks to provide fast current waveform estimation at register-transfer level (RTL). However, due to the different arrival time of internal signals, modeling the supply current of the entire logic block accurately as specific fixed templates is difficult. This paper thus proposes a levelized high-level current model for logic blocks. By merging gates with similar arrival time as a super-gate and recording its current waveforms separately, obtaining more accurate supply current waveforms is possible by using a unified model, even for multipeak cases. This paper also proposes a frequency-domain waveform transformation method to consider the effects of nonideal supply resistance on the supply current waveform. As shown in the experimental results, the peak error and waveform correlation of the proposed current model are significantly improved compared to the results of the single-stage current model. Using accurate supply current waveforms can also help obtain precise IR-drop estimation in RTL simulations for early system evaluation.