This paper introduces novel transistor reordering schemes to reduce the expected or average dynamic power dissipation in CMOS circuits. The transistor reordering is based on the signal probability values at the inputs of the gates. The paper begins with a simple analytical model for the dynamic power dissipation in a static NAND gate. The model is used to derive an algorithm for transistor reordering which reduces dynamic power dissipation. A simulation technique for accurately measuring the power dissipation in NAND gates is also presented, along with the results of the reordering algorithm. A transistor reordering algorithm for CMOS complex gates is subsequently presented. Transistor reordering is found to be an effective way to reduce power dissipation in all of these circuits, with the reduction in dynamic power dissipation compared to the worst case configuration, being as high as 50% in some instances. The limited overhead associated with transistor reordering encourage its application as a low power design technique.

We propose a new frequency hop code, called the extended hyperbolic congruential (EHC) code. The properties of the code, determined via hit array analysis, indicate almost ideal cross- and auto-ambiguity characteristics. Furthermore, the code can be defined recursively, enabling a simple hardware implementation. This makes the code attractive for code division multiple access (CDMA) communication systems.

We propose a novel testability enhancement scheme based on XOR Chain Structure. The structure is effective for improving both controllability and observability. The insertion points are selected by fast testability analysis and random pattern resistant node source tracking. Experiments with ISCAS85 benchmark circuits show that the scheme is effective. The incurred hardware overhead and performance penalty is relatively low.

A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder. The high speed operation is achieved through the Carry-Propagation-Free (CPF) accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average.

In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results indicate that transistor reordering can significantly reduce the power dissipation in CMOS NAND gates.>

We show that not all path delay faults in a prime and irredundant two-level circuit need to be tested by robust tests in order to avoid test invalidation. This finding leads to a simplified testing procedure which guarantees 100% path delay fault testability. For the collapsible multi-level circuits, we introduce the concepts of m-primeness and m-irredundancy similar to the concepts used in two-level circuits. We prove that all path delay faults in a m-prime and m-irredundant multi-level circuit are virtually testable without testing invalidation. For the uncollapsible multi-level circuits, we propose a novel modular-based path delay fault model. Using this new model, the number of target path delay faults is substantially reduced.>

In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.>

A 2- mu m CMOS locally clocked sequential microprocessor designed for a self-timed environment is described. The processor's synchronization is based on a pulse that runs through the system. The pulse is channeled through a delay block that simulates the processing time of the instruction to be executed. Since it accrues the average delay, rather than the longest delay of the instructions executed, this processor is thought to have better throughput than one with a globally distributed clock. The processor implements RISC concepts into its architecture and organization and is used for educational purposes.>

A new design for testability technique, the bit-splitting for testability enhancement in scan-based design, is presented. The idea is to split some inputs into two independent variables to make the original circuit more controllable and thus more testable. Theoretical study and experiments with two-level circuits indicate that this method can easily provide 100% Single-Path-Sensitization Path Delay Fault Testability (SPDFT). Fault coverage can also be improved for the multi-level circuits and when constrained transformations are used, multi-level circuit can also be made 100% SPDFT.>

This paper describes the design of an asynchronous pipeline structure comprising a ripple carry adder and registers placed before and after the adder. A scheme was created for monitoring the ripple of the cab through the adder. This scheme provides a means of determining when the addition is complete. The design approach uses transmission gate logic throughout. Results of SPICE simulation on the various building blocks of the circuit are presented.>

This paper discusses the design and performance of an 8-bit asynchronous multiplier. Self-timed adders with carry completion signals were implemented to create the asynchronous function of the multiplier. The technique of using bi-directional adders is incorporated in the design. One objective of this design was to estimate the longest multiplication time for a 2 mu m CMOS implementation of this 8-bit multiplier.>

A procedure for the design of robustly path-delay-fault testable two-level circuits by adding extra inputs to the circuits, using the method called Boolean space expansion is proposed. 100% path delay fault testable two-level circuits are achieved with area overhead in the range of 3% to 30%. A procedure to make the multilevel circuits fully testable is also reported. The results for several ISCAS benchmark circuits are presented.>

It is shown that the common belief that any optimized, i.e., nonredundant, circuit is easier to test than its nonoptimized counterpart is not fully justified. It is demonstrated by example that a redundant circuit may be more suitable for random testing than its optimized counterpart. A rule which specifies when redundancy is likely to enhance random testability of a two-level AND-OR gate network is formulated.>

The single-cycle protocol for integrating voice and data transmission on local area networks is introduced. This protocol is capable of maintaining low average data delays while supporting a large number of simultaneous voice calls. It makes more efficient use of silence suppression than classical time-assignment speech interpolation (TASI). Simulation results are presented and the performance with respect to other voice/data networks is discussed.>

An alternative design is found to be significantly faster than the one proposed by Hu and Smith (see ibid., vol.C-53, p.167-170, (1986)). The performance of the alternative is compared to the original. A means to buffer the signal is presented and its performance is reported. An estimate of silicon area saved versus area spent is made.>

The authors address the problem of incorporating message-based priority classes in random access protocols. The organization of these classes is based on the different packet delay requirements of higher-layer applications. A novel node-partitioning mechanism to restrict contention only to higher priority packets is introduced. The authors describe node-partitioning carrier-sense multiple access (NP-CSMA), a protocol that uses CSMA as its base access mechanism, and incorporates three priority mechanisms that influence different aspects of the channel access. These are node partitioning, priority queueing at station buffers, and prioritized persistence. A detailed simulation model is described. Simulation studies that demonstrate the effect of these mechanisms, separately and in concert, on the throughput and delay of the various priority classes are presented. It is shown how desired performance can be achieved by suitable variation of protocol parameters.>

A method is presented for estimating the maximum operating speed of NMOS self-testing circuits designed using the BILBO technique. The unique feature of this method is that the speed estimation is based only on parameters of the original design (without built-in test logic) and parameters describing the BILBO modules. Thus, a computer-aided optimization of a self-testing structure with respect to area/speed criteria can be performed without the necessity of laying out multiple self-testing versions of the original design and running timing simulation on each one.