Cloud-native technologies consisting of containers, microservices, and service meshes bring the traditional advantages of Cloud Computing like scalability, composability, and rapid deployability to the IoT Edge. An application built on the microservices architecture relies on a collection of individual containerized components offering modular services via REST or gRPC interfaces over the network. Compared to a monolithic application, the magnitude of data and control exchange between the components of a microservices application is several orders higher. Studies have shown that overheads caused by such inter-container communication are a significant hurdle in achieving the sub-50ms latencies required for 5G enabled network Edges comprised of a much smaller compute cluster, unlike the Cloud. In this paper, we present Shimmy - a shared memory-based communication interface for containers that is cleanly integrated into the Kubernetes orchestration architecture while offering significant acceleration for microservices. Results have shown a consistent 3-4x latency improvement over UDP and TCP, as much as 20x latency improvement over RabbitMQ, while significantly reducing memory and CPU usage in large data transfers as well as real-time video streaming.

Woojeong Jin, Rahul Khanna, Suji Kim, Dong-Ho Lee, Fred Morstatter, Aram Galstyan, Xiang Ren. Proceedings of the 59th Annual Meeting of the Association for Computational Linguistics and the 11th International Joint Conference on Natural Language Processing (Volume 1: Long Papers). 2021.

Pre-trained language models (PTLMs) have achieved impressive performance on commonsense inference benchmarks, but their ability to employ commonsense to make robust inferences, which is crucial for effective communications with humans, is debated.In the pursuit of advancing fluid human-AI communication, we propose a new challenge, RICA: Robust Inference using Commonsense Axioms, that evaluates robust commonsense inference despite textual perturbations.To generate data for this challenge, we develop a systematic and scalable procedure using commonsense knowledge bases and probe PTLMs across two different evaluation settings.Extensive experiments on our generated probe sets with more than 10k statements show that PTLMs perform no better than random guessing on the zero-shot setting, are heavily impacted by statistical biases, and are not robust to perturbation attacks.We also find that fine-tuning on similar statements offer limited gains, as PTLMs still fail to generalize to unseen inferences.Our new large-scale benchmark exposes a significant gap between PTLMs and human-level language understanding and offers a new challenge for PTLMs to demonstrate commonsense. 1 Logical TemplateRel(A,B,r) à Comp(Prop(A,p), Prop(B,p))

Recent works show that pre-trained language models (PTLMs), such as BERT, possess certain commonsense and factual knowledge.They suggest that it is promising to use PTLMs as "neural knowledge bases" via predicting masked words.Surprisingly, we find that this may not work for numerical commonsense knowledge (e.g., a bird usually has two legs).In this paper, we investigate whether and to what extent we can induce numerical commonsense knowledge from PTLMs as well as the robustness of this process.To study this, we introduce a novel probing task with a diagnostic dataset, NUMERSENSE 1 , containing 13.6k masked-word-prediction probes (10.5k for fine-tuning and 3.1k for testing).Our analysis reveals that: (1) BERT and its stronger variant RoBERTa perform poorly on the diagnostic dataset prior to any fine-tuning; (2) finetuning with distant supervision brings some improvement; (3) the best supervised model still performs poorly as compared to human performance (54.06% vs 96.3% in accuracy).

Firmware functional validation suffers from a series of performance limitations in practice, which in turn heavily relies on manual effort and becomes a major bottleneck of product time cycle. The requirement of repetitive run-time firmware execution for the validation environment demands novel techniques to accelerate the validation process. We propose an online firmware functional validation scheme utilizing the colored Petri net (CPN) model which can be generated automatically from the firmware source code. With simulation runs on the generated CPN models at run-time, the firmware execution path is presented and, if an error occurs, the location of error can be identified. An integrated validation tool has been designed and implemented to show the proposed validation methodology's potential and effectiveness. This tool is used in the validation of the universal serial bus (USB) initialization in unified extensible firmware interface (UEFI).

Convolutional Neural Network (ConvNet or CNN) algorithms are characterized by a large number of model parameters and high computational complexity. These two requirements have made it challenging for implementations on resource-limited FPGAs. The challenges are magnified when considering designs for low-end FPGAs. While previous work has demonstrated successful ConvNet implementations with high-end FPGAs, this article presents a ConvNet accelerator design that enables the implementation of complex deep ConvNet architectures on resource-constrained FPGA platforms aimed at the IoT market. We call the design “FeatherNet” for its light resource utilization. The implementations are VHDL-based providing flexibility in design optimizations. As part of the design process, new methods are introduced to address several design challenges. The first method is a novel stride-aware graph-based method targeted at ConvNets that aims at achieving efficient signal processing with reduced resource utilization. The second method addresses the challenge of determining the minimal precision arithmetic needed while preserving high accuracy. For this challenge, we propose variable-width dynamic fixed-point representations combined with a layer-by-layer design-space pruning heuristic across the different layers of the deep ConvNet model. The third method aims at achieving a modular design that can support different types of ConvNet layers while ensuring low resource utilization. For this challenge, we propose the modules to be relatively small and composed of computational filters that can be interconnected to build an entire accelerator design. These model elements can be easily configured through HDL parameters (e.g., layer type, mask size, stride, etc.) to meet the needs of specific ConvNet implementations and thus they can be reused to implement a wide variety of ConvNet architectures. The fourth method addresses the challenge of design portability between two different FPGA vendor platforms, namely, Intel/Altera and Xilinx. For this challenge, we propose to instantiate the device-specific hardware blocks needed in each computational filter, rather than relying on the synthesis tools to infer these blocks, while keeping track of the similarities and differences between the two platforms. We believe that the solutions to these design challenges further advance knowledge as they can benefit designers and other researchers using similar devices or facing similar challenges. Our results demonstrated the success of addressing the design challenges and achieving low (30%) resource utilization for the low-end FPGA platforms: Zedboard and Cyclone V. The design overcame the limitation of designs targeted for high-end platforms and that cannot fit on low-end IoT platforms. Furthermore, our design showed superior performance results (measured in terms of [Frame/s/W] per Dollar) compared to high-end optimized designs.

Deep neural networks have gained tremendous attention in both the academic and industrial communities due to their performance in many artificial intelligence applications, particularly in computer vision. However, these algorithms are known to be computationally very demanding for both scoring and model learning applications. State-of-the-art recognition models use tens of millions of parameters and have significant memory and computational requirements. These requirements have restricted the users of deep neural network applications to high-end, expensive, and power hungry IoT platforms to penetrate the deep learning markets. This paper presents work at the leading edge intersection of several evolving technologies, including emerging IoT platforms, Deep Learning, and Field-programmable Gate Array (FPGA) computing. We demonstrate a new minimalist design methodology that minimizes the utilization of FPGA resources and can run deep learning algorithms with over 60 million parameters. This makes particularly suitable for resource-constrained, low-end FPGA platforms.

Modern mobile pervasive applications focus on context awareness that monitors a diverse range of personal domains. In order to infer contextual information, most of these applications require the collection of raw data from sensors which are either embedded in personal smartphones or worn by the user. Critical context-aware applications rely on continuous accurate monitoring of the user's current context. Continuous sensing mechanisms in sensors cost high energy consumption to support accurate contextual detection. Hence, there is a trade-off between the classification accuracy and the energy consumption. In this paper, we exploit the advantages of Deep Neural Network (DNN) with ensemble classification of other complementary machine learning approaches to determine the best sensor sampling frequency for the recognition of a given context. DNN relies on raw data for classification while the other complementary methods (such as Decision Tree and Naïve Bayes) use feature recognition to classify data. Therefore, our approach provides a range of granularity from raw data. We prove the robustness of our approach in experiments which show high accuracy in context recognition. In addition, real experiments demonstrate the energy gains of the proposed algorithm which reach 87% reduction in energy consumption when compared to continuous sensing.

As the memory industry pushes to increase memory density, device variation is creating more defects. Furthermore, new form factors (phone, tablet, mobile and client PC) and low cost board and platform limits physical access to JTAG or TAP. Taking advantage of the x86 architecture's high functional bandwidth to memory, the quickest way to access and test memory is through CPU core, by storing and running parallel CPGC/BIST test content via CPU L3 cache, one CPGC BIST engine per memory channel. We propose a cache based testing framework that speeds up test time 60× to 170× compared to JTAG or TAP based testing using the same test content. We will present the cache based test (CBT) architecture and infrastructure (MRC/NEM setup, CPGC/IBIST), test content, results, and a side by side comparison of test time to JTAG or TAP. Finally we will discuss and compare this approach to generalized cache based tests.

As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory and IO defects and associated test and validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, a reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected to detect memory and IO defects, and combined with the software assisted repair technology to automatically repair memory cell defects on 3D stacked Wide-IO DRAM. Additionally, we also present the CPGC gate count, power, simulation, and silicon results. The reusable CPGC IP is designed to connect to a standard IP interface, which enables a quick turn-key SOC development cycle. Silicon results show CPGC can speed up validation by 5x, improve test time from minutes down to seconds, and decrease debug time by 5x including root-cause of boot failures of the memory interface. CPGC is also used in memory training and initialization, which makes it a critical part of Intel SOC.

Data Centers face considerable challenges in seamless integration of telemetry and control functions. These functions are essential to management tasks related to power capping, cooling, reliability, predictability, survivability, and adaptability control. It is therefore essential to create an infrastructure of sensors that monitors the physical properties of the dynamically changing environment. The conventional approaches to support distributed sensor data collection and control using wired solutions are static, expensive, and non-scalable. In this paper sensors and control agents supporting this telemetry are a part of a dense and noisy network that are scattered across the data centers. We present an alternative approach for this unique environment using wireless sensor network to improve data efficiency and real-time delivery. We propose genetic algorithm (GA) approach for a densely populated sensor network to dynamically construct optimal collection trees through improved channel diversity that support context aware sensor data compression and reduced latency data delivery.

Information technology systems face considerable challenges in seamless integration of telemetry and control information. These are essential to various autonomic management functions related to power, thermal, reliability, predictability, survivability, and adaptability. Sensors and control agents supporting this telemetry are a part of large multiprocessor environments that are scattered across the platform. The conventional approaches to support distributed observability and control using wired solutions are static, expensive, and non-scalable. We present an alternative approach for this unique environment that replaces static wired sensors with dynamically reconfigurable wireless sensors. It employs a genetic algorithm based approach to optimize sensor node function assignment, clustering decisions, resource distribution, and route establishment for improved control quality. Based on this new, wireless sensor network approach, we evaluate the average data-flow delay characteristics between sensor and control end-points. We also investigate the "quality of control'' by measuring the conformity of the controlled objective to platform policy specifications (like power limits).

The drive for higher performance and energy efficiency in data-centers has influenced trends toward increased power and cooling requirements in the facilities. Since enterprise servers rarely operate at their peak capacity, efficient power capping is deemed as a critical component of modern enterprise computing environments. In this paper we propose a new power measurement and power limiting architecture for main memory. Specifically, we describe a new approach for measuring memory power and demonstrate its applicability to a novel power limiting algorithm. We implement and evaluate our approach in the modern servers and show that we achieve up to 40% lower performance impact when compared to the state-of-art baseline across the power limiting range.

We propose a reduced-complexity genetic algorithm for intrusion detection of resource constrained multi-hop mobile sensor networks. Traditional intrusion detection mechanisms have limited applicability to the sensor networks due to scarce battery and processing resources. Therefore, an effective scheme would require a power efficient and lightweight approach to identify malicious attacks. The goal of this paper is to evaluate sensor node attributes by measuring the perceived threat and its suitability to host local monitoring node (LMN) that acts as trusted proxy agent for the sink and capable of securely monitoring its neighbors. Security attributes in conjunction with genetic algorithm jointly optimizes the placement of monitoring nodes (i.e., LMN) by dynamically evaluating node fitness by profiling workloads patterns, packet statistics, utilization data, battery status, and quality-of-service compliance.

Third generation Intel®IBIST (IBIST) is the first full featured edition of what was originally envisioned in 1999. The objective was to create a standard infrastructure for validating, debugging, and testing high speed IOs (Input/Output) which could be supported by a common software toolset. This vision was realized in 2009 on Intel products. The IBIST methodology has become a standard at Intel. Today, IBIST is utilized from the very beginning of the product verification including initial power-on silicon debug. It a staple throughout the back-end product validation process and is also utilized in end-customer validation and high volume testing. Intel's platform reliability, availability, serviceability(collectively referred to as RAS) architecture exploits the technology on a number of fronts as well. The content of this paper includes an overview of the problems which mandated this paradigm shift away from the historical IO testing methodologies, an IBIST architectural overview, and the key application spaces addressed by this technology.

We propose a reduced-complexity genetic algorithm for dynamic deployment of resource constrained multi-hop mobile sensor networks. The goal of this paper is to achieve optimal coverage and improved battery life using dynamic power scaling (DPS) and improved fitness function. DPS exploits idle times, packet delay guarantees, performance and workload data using additional controls related to sensor power states and transmission power. The dynamic power scaling in conjunction with genetic algorithm jointly optimizes power states and topologies by dynamically monitoring workloads, packet arrivals, utilization data and quality-of-service compliance. This results in minimization of the power consumption of the sensor system while maximizing the sensor objectives.

We propose a reduced-complexity genetic algorithm for secure and dynamic deployment of resource constrained multi-hop mobile sensor networks. Mobility and security are relatively expensive operations since they involve both communication and computation. Furthermore, these operations have to co-exist with optimal node and route assignments. The goal of this paper is to achieve optimal secure coverage and improved battery life using dynamic re-locatability. The genetic algorithm is used to adaptively configure optimal position and security attributes by dynamically monitoring network traffic, packet integrity, and battery usage. This results in minimization of the power consumption of the sensor system while maximizing the sensor objectives (coverage and exposure).

Ad hoc wireless networks are more vulnerable to malicious attacks than traditional wired networks due to the silent nature of these attacks and the inability of the conventional intrusion detection systems (IDS) to detect them. These attacks operate under the threshold boundaries during an intrusion attempt and can only be identified by profiling the complete system activity in relation to a normal behavior. In this paper we discuss a control-theoretic Hidden Markov Model (HMM) strategy for intrusion detection using distributed observations across multiple nodes. This model consists of a distributed HMM engine that executes in a randomly selected monitor node and functions as a part of the feedback control engine. This drives the defensive response based on hysteresis to reduce the frequency of false positives, thereby avoiding inappropriate ad hoc responses.

In this paper we propose a reduced-complexity genetic algorithm for optimization of multi-hop sensor networks. The goal of the system is to generate optimal number of sensor-clusters with cluster-heads. It results in minimization of the power-consumption of the sensor-system while maximizing the sensor objectives (coverage and exposure). The genetic algorithm is used to adaptively create various components such as cluster-members, cluster-heads, and next-cluster. These components are then used to evaluate the average fitness of the system based on the sequence of communication links towards the sink.

In an era of cooperating ad hoc networks and pervasive wireless connectivity, we are becoming more vulnerable to malicious attacks. Many of these attacks are silent in nature and cannot be detected by the conventional intrusion detection system (IDS) methods such as traffic monitoring, port scanning, or protocol violations. These sophisticated attacks operate under the threshold boundaries during an intrusion attempt and can only be identified by profiling the complete system activity in relation to a normal behavior. In this paper we discuss a hidden Markov model (HMM) strategy for intrusion detection using a multivariate Gaussian model for observations that are then used to predict an attack that exists in a form of a hidden state. This model is comprised of a self-organizing network for event clustering, an observation classifier, a drift detector, a profile estimator, a Gaussian mixture model (GMM) accelerator, and an HMM engine. We use this method to predict the intrusion states based on observation deviation from normal profiles or by fitting it into an appropriate attack profile.

In order to achieve high video coding efficiency, a new motion estimation and compensation algorithm is proposed based on Genetic Algorithm. This algorithm exploits the uniformity and correlation in the properties of the cluster of blocks called Super-Block. These Super-Blocks have adaptive boundaries that are used to partially generate initial population for fast convergence to global minimum. Rest of the population is generated using pure Random Number Generator (RNG). This population then generates offspring which then competes within itself by the virtue of it’s fitness to survive into the next generation. The fitness value in each generation is calculated by comparing the reference frame with the predicted frame. The algorithm stops after convergence or when maximum generations are reached. This algorithm compares well against conventional algorithms like FSA (Full Search Algorithm), One-Step Method or N-Step Method in terms of number of searches, complexity, robustness and scalability.