This paper presents a DFT-IDFT-based minimum-segment calibration technique for SAR ADCs, specifically targeting capacitor mismatch-induced nonlinearity under incoherent sampling conditions. By employing multi-term cosine-sum window functions, spectral leakage is significantly suppressed, enabling accurate digital estimation of nonlinear bit-weight errors. The proposed method employs lookup tables (LUTs) to integrate DFT/IDFT and windows, greatly simplifying ADC error extraction, while employingLDL${}^{\mathbf {T}}$decomposition for numerically stable least-squares estimation. A novel metric, Maximum Single-Tone Offset Attenuation (MSTOA), is introduced to evaluate window functions’ efficacy in suppressing spectral leakage. Among digital calibration methods, the minimum-segment approach achieves substantial improvement in calibration accuracy while maintaining comparable computational complexity. The non-iterative, one-shot error extraction method eliminates convergence delays inherent in iteration-based methods. Additionally, built-in self-test (BIST) capability enables concurrent dynamic performance evaluation. Measurement results from a 20-bit 1-MS/s prototype implemented in 180-nm CMOS demonstrate that post-calibration SNDR/SFDR can be improved by 22.7dB and 27.3 dB, respectively.

This paper presents a mode-reconfigurable 2nd-order noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) featured with the ability of optimizing the noise transfer function (NTF) synchronously. Three operation modes, the energy-saving (ES) mode, the normal (NM) mode, and the high-resolution (HR) mode, can be supported by reconfiguring the resolution of the internal SAR ADC (N${}_{\mathrm {SAR}}$) and the oversampling rate (OSR), while the NTF optimization is realized by modulating locations of zeros and poles in the context of a specific mode to enhance the NS effect. The prototype ADC is fabricated in a 180-nm CMOS and operates under a 1.8-V supply. Operating at 5MS/s sampling rate, the ADC’s OSR can be configured as 8 or 16 in different operation modes, so its bandwidth can be configured as 312.5kHz or 156.25kHz. With NSARand OSR reconfigured to be 8-bit and 8 for the ES mode, it achieves a signal-to-noise and distortion ratio (SNDR) of 80.3dB and consumes$201\mu $W. Attributing to the NTF optimization, 27% power saving can be reached in the ES mode with respect to that when the optimization were disabled for the same SNDR. In the HR mode, NSARand OSR are set to be 9-bit and 16, respectively. And a SNDR of 93.3dB is obtained at the expense of consuming$280\mu $W. It is evidenced that the SNDR can be boosted by 6.4dB owe to the NTF optimization, resulting in an optimal SNDR-based Schreier figure-of-merit (FoM${}_{\mathrm {S}}$) of 180.8dB for the ADC. The values for NSARand OSR are determined to be 9-bit and 8 for the NM mode, and the achievable SNDR is 88.2dB. The occupied core area is 0.537 mm2.

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR’s, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18-$\mu \text{m}$CMOS process, the prototype occupies 1.01 mm2. On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

This brief proposes a time-domain second-order noise shaping analog-to-digital converter (ADC). It employs a voltage-to-time converter (VTC) in tandem with a second-order noise shaping time-to-digital converter (TDC), which realizes the goal of reducing the power consumption and accommodating different resolutions by configuring locations of poles of the transfer function. Note that the time-register constructed TDC, which performs the signal processing function in the time domain, is implemented with digital cells thoroughly. In this way, the proposed architecture can be more friendly to the increasingly scaled process. The reconfigurable architecture enables to obtain the target signal-to-noise-and-distortion ratio (SNDR) with decreased oversampling ratio (OSR), which improves energy efficiency relatively. In addition, compared with the conventional CMOS gated delay cell, the proposed single fan-out (SFO) gated delay cell is featured with lower power dissipation and shorter delaying time. The prototype is implemented in a 0.18-$\mu \text{m}$CMOS technology to demonstrate the validity of this proposed time-domain ADC. It achieves 64.5-, 56.1-, and 51.2-dB SNDR in 0.025-, 0.05-, and 0.1-MHz bandwidth on conditions of the OSR being 200, 100, and 50, respectively.

Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.