We consider the problem of duplicate document detection for search evaluation. Given a query and a small number of web results for that query, we show how to detect duplicate web documents with precision ~0.91 and recall ~77. In contrast, Charikar's algorithm, designed for duplicate detection in an indexing pipeline, achieves precision ~0.91 but with a recall of ~0.58. Our improvement in recall while maintaining high precision comes from combining three ideas. First, because we are only concerned with duplicate detection among results for the same query, the number of pairwise comparisons is small. Therefore we can afford to compute multiple pairwise signals for each pair of documents. A model learned with standard machine-learning techniques improves recall to ~0.68 with precision ~0.90. Second, most duplicate detection has focused on text analysis of the HTML contents of a document. In some web pages the HTML is not a good indicator of the final contents of the page. We use extended fetching techniques to fill in frames and execute Java script. Including signals based on our richer fetches further improves the recall to ~0.75 and the precision to ~0.91. Finally, we also explore using signals based on the query. Comparing contextual snippets based on the richer fetches improves the recall to ~0.77. We show that the overall accuracy of this final model approaches that of human judges.

The paper describes the analysis of worst case execution times for a class of acyclic processes that can express precedence constraints and internal computational delays. The motivation for our work comes from hardware designs where a scheduler allocates exclusive access to a memory bus. Blocks that execute concurrently generate read and write requests. The timing of these requests may depend on factors such as bus contention, internal buffering, internal timing delays, and pipelining. Adaptations of our proposed method have enabled the verification of the timing performance of all subprocesses of an industrial MPEG-2 audio/video decoder chip. The method is accurate enough to produce guaranteed deadlines that are within 1% of those obtained through performance simulation.

We describe a new implementation of HYTECH, a symbolic model checker for hybrid systems. Given a parametric description of an embedded system as a collection of communicating automata, HYTECH automatically computes the conditions on the parameters under which the system satisfies its safety and timing requirements. While the original HYTECH prototype was based on the symbolic algebra tool Mathematica, the new implementation is written in C++ and builds on geometric algorithms instead of formula manipulation. The new HYTECH offers a cleaner and more expressive input language, greater portability, superior performance (typically two to three orders of magnitude), and new features such as diagnostic error-trace generation. We illustrate the effectiveness of the new implementation by applying HYTECH to the automatic parametric analysis of the generic railroad crossing benchmark problem and to an active structure control algorithm.

Three algorithms for checking the emptiness of a timed transition system have been implemented. The first algorithm performs a straightforward reachability analysis on sets of states of the system, rather than on individual states. This corresponds to stepping symbolically through the system many states at a time. The other two algorithms are minimization algorithms. These simultaneously perform reachability analysis and minimization from an implicit system description. The paradigm for verification is to test for the emptiness of the set of all timed system executions that violate a requirements specification. Preliminary results over two simple examples indicate that memory usage is a more limiting factor than time.>

The authors formulate and analyze a controller synthesis problem for a plant which must meet certain hard real-time deadlines. In this timed input-output control problem, the plant is modeled by finite timed traces. The authors provide necessary and sufficient conditions for the existence of a timed input-output controller. The results are based in part on the supervisory control theory of P.J. Ramadge and W.M. Wonham. When the plant and the closed-loop specification are represented by deterministic limited automata, the synthesis problem can be solved. The synthesis procedure and the synthesized supervisor are polynomial in the number of automata states and exponential in the timing information.>