In this paper, low threshold voltage (V/sub t/) "natural" transistors, available in some n/sup +//p/sup +/ dual poly gate CMOS/BiCMOS processes, are proposed for low voltage switched capacitor circuit design. The impact of the subthreshold off-current of these low V/sub t/ devices on the performance of analog switched-capacitor (SC) circuits is analyzed. Methods for reducing the subthreshold off-current in analog switches are discussed and two new switch topologies (series transmission gate and composite switch) addressing this problem are presented.

It is demonstrated that a filter-bank structure can be designed to significantly reduce the effect of intermodulation distortion. This gives it an important advantage over other structures in radio systems. The principle is explained, and supported with Volterra analysis and simulation.

A new technique for designing an LC bandpass delta-sigma modulator is presented. This method is based on pulse shaping of a DAC output signal such that one can realize a desired (arbitrary) loop transfer function. Especially for higher-order modulators where extra LC sections are added, sufficient number of parameters are provided in the feedback loop. It is shown that by creating more degrees of freedom one can achieve the maximum SNR in a given modulator order without constraining the noise transfer function of the modulator.

With the growing demand for high-speed transmission of digital data, there is a challenge for utilizing the existing copper plant as the transmission medium, especially for short-hop links. This medium offers a lower cost to a fiber medium, but requires more sophisticated electronics to account for electromagnetic emissions, cross-talk, and cable loss. These include pulse shaping filters, cross-talk cancelers, and equalizers. To maintain system cost at a minimum, analog solutions are preferred. A continuous-time tunable biquad implemented in a 0.8 /spl mu/m BiCMOS process and configured as an adaptive pulse-shaping filter is described. The biquad is tunable over the range 10-230 MHz with variable Q factors. It is composed of five transconductance-C integrators each dissipating a static power of 10 mW at 5 V. A method for adapting the filter's pole-frequency and Q-factor while servicing 100 Mb/s NRZ data is presented together with experimental results.

A floating gate charge-sharing circuit that can be electrically programmed for precise positive and negative voltage changes, and can be implemented in a standard CMOS VLSI process is presented. With the advantage of its long-term charge-retention, the floating gate charge-sharing circuit is suitable for providing a compact, non-volatile and high-precision analog trimming method to trim the offset voltage resulting from unavoidable mismatches in analog circuits such as op-amps and comparators.>

A novel two-dimensional z-transform approach to the analysis of analog/digital (A/D) converter nonlinearity is presented. It was primarily developed to study the stability behavior of an adaptive self-trimming technique for flash and multi-stage A/D converters, but has more general applicability.>

A novel self-trimming algorithm for A/D converters has been presented which continually trims thresholds in the flash A/D subconverters of two-stage and pipelined A/D converters. Roughly speaking, it trims thresholds up or down by small increments in such a way as to smooth out irregularities in the code density. This paper presents the mathematical analysis and design of the algorithm. The algorithm was analyzed by a novel two-dimensional z-transform (Z-T), which can be used to demonstrate its stability, predict convergence rate, and which can be used to give a frequency-domain interpretation of the distinct properties of differential and integral nonlinearity.>

A new architecture is proposed for a single-chip digital radio receiver. This architecture has several advantages over the direct-conversion architecture that has been gaining interest for use in single-chip designs. A non-zero quadrature IF reduces the image problem and eliminates concerns about self-EMI and 1/f noise. A complex bandpass filter embedded in a delta-sigma loop allows the A/D conversion to be performed directly on the pair of quadrature outputs from the mixer.>

A systematic technique for designing a continuous-time sigma-delta modulator (/spl Sigma//spl Delta/M) is presented. The continuous-time /spl Sigma//spl Delta/ open-loop transfer function is obtained by the pulse-invariant transformation of its discrete-time equivalent. This method results in an inherently stable /spl Sigma//spl Delta/M and does not need any loss factor to make the modulator stable, and so provides the maximum achievable signal-to-noise ratio. Properties of the continuous-time /spl Sigma//spl Delta/M are described. The technique has been applied to-conventional lowpass and bandpass /spl Sigma//spl Delta/Ms, and a general-fourth-order bandpass example is given to illustrate the theory.>

The effects of DC offsets on four variations of the stochastic gradient algorithm are analyzed to determine the most appropriate algorithm for hardware implementation. The output mean squared error (MSE) performance in the presence of DC offsets is evaluated and compared with computer simulations for each of the algorithms assuming a Gaussian input distribution.>

An application for adaptive nonlinear filters, adaptive linearization of a loudspeaker, is presented. An adaptive predistortion linearization scheme is used for linearizing a loudspeaker. A model of a direct radiator loudspeaker is developed and studied which takes into account two principal sources of nonlinear distortions: nonlinearity in the suspension system and inhomogeneity in the flux density. Based on this model, simulations of the proposed method were performed. The results show that nonlinear distortions of a loudspeaker can be reduced significantly.>

The stability of a single-quantizer Sigma Delta modulator in terms of its noise transfer function is studied. It is shown that stability is conditional upon the input signal, and an explicit formula for the set of all inputs which result in stable behavior is given. In addition, the authors compare the set of modulators stable with zero input to the sets given by several existing rules of thumb and find that these criteria are neither necessary, nor in some cases sufficient, to ensure stability.>

An algorithm called heuristic spanning creates parallelism by simultaneously investigating different areas of the plausible combinatorial search space. It is used to replace the high-temperature portion of simulated annealing. The low-temperature portion of simulated annealing is sped up by a technique called section annealing, in which placement is geographically divided and the pieces are assigned to separate processors. Each processor generates simulated-annealing-style moves for the cells in its area and communicates the moves to other processors as necessary. Heuristic spanning and section annealing are shown experimentally to converge to the same final cost function as regular simulated annealing. These approaches achieve significant speedup over uniprocessor simulated annealing, giving high-quality VLSI placement of standard cells in a short period of time.>