Demo Data from EDBT 2026 / reviewers in the wild / expert
Chen-Liang Fang
dblp:78/2351
· DBLP profile ↗
10ranked-venue papers
4as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 7 · 2 first-authorSystems, architecture and hardware · 3 · 2 first-authorArtificial intelligence and machine learning · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
timing optimization |
0.0 | 2 | 1995 | Timing optimization by gate resizing and critical path identification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 Timing Optimization By Gate Resizing And Critical Path Identification · DAC 1993 |
Electronic design automation › timing analysis
critical path generation |
0.0 | 1 | 1995 | Timing optimization by gate resizing and critical path identification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation › circuit sizing
gate resizing |
0.0 | 1 | 1995 | Timing optimization by gate resizing and critical path identification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1995 | Timing optimization by gate resizing and critical path identification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1995 | Timing optimization by gate resizing and critical path identification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1995 | Timing optimization by gate resizing and critical path identification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation › physical design
gate sizing |
0.0 | 1 | 1993 | Timing Optimization By Gate Resizing And Critical Path Identification · DAC 1993 |
Electronic design automation
physical design |
0.0 | 1 | 1993 | Timing Optimization By Gate Resizing And Critical Path Identification · DAC 1993 |
Methods — techniques the papers use, named apart from their topics
benefit functions · 0.0PODEM · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Fault tolerant Web Services
Chen-Liang Fang, Deron Liang, Fengyi Lin, Chien-Cheng Lin |
J. Syst. Archit. | 1 |
| 2006 | A Portable Interceptor Mechanism on SOAP for Continuous AuditabstractWeb services has become popular in modern distributed applications, and the SOAP technology currently is the most used in Web services. Recent middleware research works widely use interception approach for many problem domains, for example fault tolerance, continuous audit {CA), security etc. Instead of providing a portable interceptor as CORBA does, SOAP 1.2 provides an intermediary mechanism. Due to backward compatibility issue, we found intermediary mechanism is not a feasible solution for interception. Furthermore, our use case analysis found that CORBA Portable Interceptor functionality does not fulfill all requirements of continuous audit. This motivates us to develop a new portable interceptor mechanism (PIM) on SOAP for CA. In this paper, we propose a PIM on SOAP to meet the interception requirements for Web services. Our PIM includes portable interceptor management in SOAP engine and portable interceptor interface definitions. Chen-Liang Fang, Deron Liang, Fengyi Lin, Chien-Cheng Lin, William C. Chu |
APSEC | 1 |
| 2005 | A Chinese Text Mining Application: An Automatic Answer Reply to Customers' E-mail Queries Model
Ju-Yu Huang, Huey-Ming Lee, Chen-Liang Fang |
SEKE | 3 |
| 2004 | A Nested Invocation Suppression Mechanism for Cctive Replicated SOAP SystemsabstractThe simple object access protocol (SOAP) is recognized as a more promising middleware for electronic commerce applications among other leading candidates such as CORBA. Many recent polls reveal however that security and reliability issues are major concerns that discourage people from engaging in electronic commerce transactions. We note that these issues are not adequately addressed in the current standard, i.e., SOAP 1.2. Active replication is a common approach to building readily available and highly reliable distributed software applications. The redundant nested invocation (RNI) problem arises when servers in a replicated group issues nested invocations to other server groups in response to a client invocation. Automatic suppression of RNI from active group is always a desirable function, yet this function usually requires careful if not complex design. The design complexity increases if the system involves multithreading implementation. Existing solutions either solve RNI problem for single-threading cases or solve multithreading cases at the expense of portability. In this work, we propose a mechanism to perform auto-suppression of redundant nested invocation on an active replication fault tolerant Web service. Our approach is portable so that the Web service running on our platform is able to interact with any other SOAP applications. Our preliminary experiments show that the proposed auto-suppression mechanism is efficient in most cases. Chen-Liang Fang, Deron Liang, Fengyi Lin |
APSEC | 1 |
| 2003 | Fault tolerant web serviceabstractZwass (1996) suggested that middleware and message service is one of the five fundamental technologies used to realize electronic commerce (EC). The simple object access protocol (SOAP) is recognized as a more promising middleware for EC applications among other leading candidates such as CORBA. Many recent polls reveal however that security and reliability issues are major concerns that discourage people from engaging in EC transactions. We notice that the fault-tolerance issue is somewhat neglected in the current standard, i.e., SOAP 1.1. We therefore propose a fault tolerant Web service called fault-tolerant SOAP or FT-SOAP through which Web services can be built with higher resilience to failure. FT-SOAP is based on our previous experience with an object fault tolerant service (OFS) [Liang, D. et al., (1999)] and OMG's fault tolerant CORBA (FT-CORBA). There are many architectural differences between SOAP and CORBA. One of the major contributions of this work is to discuss the impact on FT-SOAP design due to these architectural differences. Our experience shows that Web services built on a SOAP framework enjoy higher flexibility as opposed to those built on CORBA. We also point out the limitations of the current feature sets of SOAP 1.1. We believe our experience is valuable not only to the fault-tolerance community, but also to other communities as well, in particular, to those who are familiar with the CORBA platform. Deron Liang, Chen-Liang Fang, Chyouhwa Chen, Fengyi Lin |
APSEC | 2 |
| 2002 | A nested invocation suppression mechanism for active replication fault-tolerant CORBAabstractActive replication is a common approach to building highly available and reliable distributed software applications. The redundant nested invocation (RNI) problem arises when servers in a replicated group issues nested invocations to other server groups in response to a client invocation. Automatic suppression of RNI is always a desirable solution, yet it is usually a difficult design issue. If the system has multithreading (MT) support, the difficulties of implementation increase dramatically. Intuitively, to design a deterministic thread execution control mechanism is a possible approach. Unfortunately, some modern operating systems implement threads on the kernel level for execution fairness. For the kernel thread case, modification on thread control implies modifying the operating system kernel. This approach loses system portability which is one of the important requirements of CORBA or middleware. In this work, we propose a mechanism to perform the auto-suppression of redundant nested invocation in an active replication fault-tolerant (FT) CORBA system. Besides the mechanism design, we discuss the design correctness semantic and the correctness proof of our design. Deron Liang, Chen-Liang Fang, Chyouhwa Chen, Fengyi Lin |
APSEC | 2 |
| 2002 | A Nested Invocation Suppression Framework for Active Replication Fault-Tolerant CORBAabstractActive replication is a common approach to building highly available and reliable distributed software applications. The redundant nested invocation (RNI) problem arises when servers in a replicated group issue nested invocations to another server group in response to a client invocation. Automatic suppression of RNI is always a desirable solution, yet it is usually a difficult design issue. In this research, we propose a new determinism reference model based on accomplishing the verification process in a more systematic manner The proposed determinism reference model consists of four levels, namely: ideal determinism, isomorphic determinism, similar determinism, and non-determinism. We consider a class of multi-threading CORBA environments to demonstrate the power of the proposed determinism reference model. Deron Liang, Chen-Liang Fang |
COMPSAC | 2 |
| 1999 | A fault-tolerant object service on CORBA
Deron Liang, Chen-Liang Fang, Shyan-Ming Yuan, Chyouhwa Chen, Gene Eu Jan |
J. Syst. Softw. | 2 |
| 1995 | Timing optimization by gate resizing and critical path identificationabstractDue to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, use of a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control the hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM, called /spl tau/PODEM, ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitively reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing.> Chen-Liang Fang, Wen-Ben Jone |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1993 | Timing Optimization By Gate Resizing And Critical Path IdentificationabstractDue to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically.Both more functions and higher speed are required in modern VLSI engineering.Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design.Here, we propose an efficient method for timing optimization using gate resizing.To control hardware overhead, a minimum (or as Wen-Ben Jone, Chen-Liang Fang |
DAC | 2 |