The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-induced variation is reduced by 3dB, which improves chip-limited yield. The parallel VCOs trade off circuit area and power in exchange. The parallelism advantages in analog and digital systems are compared.

This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data-driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates systematic process variations on die-to-die and wafer-to-wafer levels is also presented. The proposed framework enables translations of interactions among technology, product, and model, and facilitates collaborative efforts accordingly.

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-μm SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOMT) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOMT of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is -126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 μW.

A static frequency divider by 8 was fabricated in a 120 nm SOI technology. The highest operation frequency achieved is 8.25 GHz at 1.5 V power supply. The lowest core power consumption achieved is 0.016 mW at 4 GHz when the lowest operating voltage supply of 0.75 V is used.

This paper presents a design for an ASK-based IF-stage. This IF-stage was designed as part of a single-chip ISM band short range wireless telemetry system. The design was fabricated in 0.5 /spl mu/m CMOS process. Two main components of the IF-block are discussed in this paper. Measurement and simulation results are provided for the AGC circuit and the ASK detector. The measured dynamic range for the AGC is 40 dB at a 10 MHz IF frequency. The ASK detector was designed to operate at 1 Mb/s for the same IF frequency. A fully differential signal path is maintained throughout the design to reduce the impact of substrate and supply fluctuations. Measurement and simulation results are presented to verify the design.