Today it is evident that ATM technology will have its role in the future of internetworking. Two major Internet backbone service providers, Sprint and MCI, have marketed their investments in ATM as a way to push more bandwidth into their Internet infrastructures. Regardless of whether ATM technology will thrive in the WAN or LAN, it is also evident that the Internet Protocol (IP), which has been the glue of the Internet allowing it to endure exponential growth, must be well supported over ATM. IP multicast (protocol extensions to IP that allow IP packets from one source to be distributed to multiple destinations) is an essential part of IP which has allowed multimedia applications, for example, to more efficiently use Internet resources. In this paper we describe an implementation of one model of supporting IP multicast over ATM, the Multicast over ATM model developed by the IETF (Armitage, 1996). We discuss empirical measurements gathered in a testbed with both a WAN and a LAN component that give insights into the behavior of this model. We detail some of the shortcomings of this model and discuss potential modifications to improve it. Ideas for other approaches to IP multicast over ATM are also described.

Small switching elements are the key components of multistage interconnection networks (MINs) used in multiprocessors and in high speed switching fabrics. Clock design for synchronous MINs is an important issue. The existing models assume that the clock period consists of two parts. The control messages are transferred between switching stages during the first part, and the actual data transfer takes place during the second part. We propose a new control design for single queue MINs that reduces the duration of the clock period by making use of output buffers and acknowledgments. The reduction in the clock period comes from the addition of two-unit output buffers, introducing a sophisticated hardware control mechanism, and sacrificing the FIFO feature. We develop an analytical model to compare its performance with the existing designs reported in the literature. We validate our model with extensive simulation studies.