Approximate computing has emerged as a promising paradigm for error-tolerant applications, enabling power-efficient designs with minimal compromise in output quality. In such applications, division units are often among the most complex and latency-critical components, contributing significantly to overall power consumption. Therefore, approximating the division module offers substantial potential for improving power efficiency. This paper introduces a novel exact divider architecture based on low-power full adders, which achieves reduced power consumption and occupies less area compared to conventional exact divider structures. To further enhance area and power efficiency, three different approximate divider architectures are proposed. These designs apply approximation strategies in three ways: row-wise, column-wise, and a combination of both. All three approximate architectures are implemented using the proposed approximate full adder design. The proposed approximate full adder reduces computational complexity while maintaining a high level of accuracy within the divider architecture. Experimental results demonstrate that the proposed exact and approximate dividers reduce power consumption by up to 20% and 35%, respectively, compared to traditional exact and existing approximate divider architectures, all while maintaining better accuracy. Additionally, the proposed approximate divider achieves up to a 48% reduction in area usage. Evaluation using image processing applications further confirms that the proposed designs outperform existing approximate dividers in both efficiency and output quality.

Posit number system is an emerging number system which aims to be a competitor to the existing IEEE floating-point number system. The posit number system aims to overcome certain inherent flaws associated with the floating-point system and improve the performance of VLSI arithmetic circuits. Recent studies indicate that posit number system has the potential to vastly improve the performance of deep neural network hardware. As a result, posit arithmetic has become an important area of research. Among all the arithmetic operations in computer arithmetic, the most frequently used is multiplication. Multiplication is ubiquitously used in applications varying from image processing, signal processing to neural networks and machine learning. Multiplication also has an extremely high cost in terms of power, area and delay and thus extensive research work goes into optimization of the above parameters. In this brief, two new multiplier designs based on the Modified Booth algorithm have been proposed- P1 and P2 with novel control logic circuits to reduce dynamic power dissipation. The proposed work also involves the design of a novel sign extension with lower gate count for the Modified Booth Algorithm. Results have indicated that the proposed designs P1 and P2 achieve an improvement of 24% and 22% respectively in the PDP over the existing designs.

The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed, keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2's complement and 10's complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable to facilitate both BCD and Binary operations. Simulation results show that the proposed architecture is 13.6% better in terms of delay than the existing design.

In this paper, a new low power and configurable resolution two step flash ADC is proposed. Comparators of conventional flash ADC are replaced with CMOS inverters whose threshold can be varied dynamically. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused parallel inverters to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADC is capable of operating at 8-bit, 10-bit, and 12-bit precision and at a supply voltage of 2.5V; it consumes 16mW at 12-bit, 12mW at 10-bit and 8mW at 8-bit resolution. The sampling frequency ranges from 0.5 to 1.0 GSPS, and the ADC has a DNL

Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3,2), (7,3), (15,4) and (31,5) counters capable of operating at ultra-low voltages are presented. Based on these counters, a generalized architecture is derived for large (m, n) parallel counters. The proposed architecture lays emphasis on the use of multiplexers and a combination of CMOS and transmission gate logic in arithmetic circuits that result in high speed and efficient design. The proposed counter designs have been compared with existing designs and are shown to achieve an improvement of about 45% in delay and a reduction of about 25% in power consumption.

Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of these operations has been widely discussed in literature. A redundant binary to binary converter lies directly within the critical path of any operations in this number system, thereby dictating the performance of the overall circuit. In this paper, a new redundant binary to binary converter is proposed using the logic of prefix adders. Though carry propagation is still present in the proposed implementation, the latency has been reduced to O (log n) by the use of sparse-tree networks. The architecture of the proposed converter has been compared (both qualitatively as well as quantitatively) with the existing designs and is shown to achieve an efficiency of 52% in the overall delay and reduction of 36% in power-delay product.