Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation.

An interval-mathematic approach is presented for frequency-domain simulation and sensitivity analysis of linear analog circuits under parameter variations. With uncertain parameters represented as intervals, bounding frequency-domain responses is formulated as the problem of solving systems of linear interval equations. The formulation is based on a variant of modified nodal analysis, and is particularly amenable to interval analysis. Some characterization of the solution sets of systems of linear interval equations are derived. With these characterizations, an elegant and efficient algorithm is proposed to solve systems of linear interval equations. While the widely used Monte Carlo approach requires many circuit simulations to achieve even moderate accuracy, the computational cost of the proposed approach is about twice that of one circuit simulation. The computed response bounds contain provably, or are usually very close to, the actual response bounds. Further, sensitivity under parameter variations can be computed from the response bounds at minor computational cost. The algorithms are implemented in SPICE3F5, using sparse-matrix techniques and tested on several practical analog circuits.

This paper describes a method to improve the efficiency of nonlinear DC fault simulation. The method uses the Newton-Raphson algorithm to simulate each faulty circuit. The key idea is to order the given list of faults in such a way that the solution of previous faulty circuit can serve as a good initial point for the simulation of the next faulty circuit. To build a good ordering, one step Newton-Raphson iteration is performed for all the faulty circuits once, and the results are used to quantify how faulty circuits and the good circuit are close in their behaviors. With one-step Newton-Raphson iteration implemented by Householder's formula, the proposed method has virtually no overhead. Experimental results on a set of 36 MCNC benchmark circuits show an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation.

Efficient methods have been developed for fault simulation of linear analog circuits. However, DC fault simulation of nonlinear analog circuits-a more practically-relevant problem-remains largely unexplored. In this paper, we propose an one-step relaxation approach to nonlinear DC fault simulation. In this approach, only one Newton-Raphson iteration is performed for the faulty circuit with the DC solution of the good circuit as the initial point, and the results are used to approximate the actual results of exact fault simulation. With one-step relaxation implemented using Householder's formula, the proposed approach is numerically stable, and computationally efficient. It has a very simple circuit interpretation: the nonlinear circuit under test is modeled by a linearized circuit at its operating point, and faults are modeled as faults in the linearized circuit. Experiment results have demonstrated that the proposed approach achieves almost the same fault coverage as exact fault simulation for 29 MCNC Circuit Simulation Workshop benchmark circuits.

Fault-driven analog and mixed-signal testing calls for rapid fault simulationtechniques. A problem that has not been addressed effectivelyby existing research is that circuit parameters have tolerance ranges.In this paper, we propose representing parameters under variations asintervals, and present an efficient algorithm - based on interval analysisand Householder's formula - to compute the worst-case responsebounds of good and faulty linear(ized) circuits under parameter variations.Our approach takes CPU time comparable to one nominal circuitsimulation, and always produces correct and conservative results. Thealgorithm has been implemented into SPICE3F5. Experimental resultsshow an acceptable accuracy.