Demo Data from EDBT 2026 / reviewers in the wild / expert
Naveen Kumar 0002
dblp:78/2996-2
· DBLP profile ↗
7ranked-venue papers
2as first author
0since 2021 · last 2012
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 1 first-authorSoftware engineering, systems software and programming languages · 5 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 87% Parallel and multicore computing · 13% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › general-purpose processor architecture
hybrid processor |
0.1 | 1 | 2012 | BlockChop: Dynamic squash elimination for hybrid processor architecture · ISCA 2012 |
Processor architecture and microarchitecture
speculative execution |
0.1 | 1 | 2012 | BlockChop: Dynamic squash elimination for hybrid processor architecture · ISCA 2012 |
Parallel and multicore computing › thread-level parallelism
multithreaded workloads |
0.0 | 1 | 2012 | BlockChop: Dynamic squash elimination for hybrid processor architecture · ISCA 2012 |
Methods — techniques the papers use, named apart from their topics
retrial · 0.1interpretation · 0.1dynamic retranslation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | BlockChop: Dynamic squash elimination for hybrid processor architectureabstractHybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative optimization. As we move to a multicore hybrid design, fine grained conflicts for shared data can violate the atomicity requirement of these blocks and lead to expensive squashes and rollbacks. However, as these atomic regions differ from those used in checkpointing and transactional memory systems, the extent of this potentially prohibitive problem remains unclear, and mechanisms to mitigate these squashes dynamically may be critical to enable a highly performant multicore hybrid design. In this work, we investigate how multithreaded applications, both benchmark and commercial workloads, are affected by squashes, and present dynamic mechanisms for mitigating these squashes in hybrid processors. While the current wisdom is that there is not a significant number of squashes for smaller atomic regions, we observe this is not the case for many multithreaded workloads. With region sizes of just 200 - 500 instructions, we observe a performance degradation ranging from 10% to more than 50% for workloads with a mixture of shared reads and writes. By harnessing the unique flexibility provided by the software subsystem of hybrid processor design, we present BlockChop, a framework for dynamically mitigating squashes on multicore hybrid processors. We present a range of squash handling mechanisms leveraging retrials, interpretation, and retranslation, and find that BlockChop is quite effective. Over the current response to exceptions and squashes in a hybrid design, we are able to improve the performance of benchmark and commercial workloads by 1.4x and 1.2x on average for large and small region sizes respectively. Jason Mars, Naveen Kumar 0002 |
ISCA | 2 |
| 2009 | Transparent Debugging of Dynamically Optimized CodeabstractDebugging programs at the source level is essential in the software development cycle. With the growing importance of dynamic optimization, there is a clear need for debugging support in the presence of runtime code transformation. This paper presents a framework, called DeDoc, and lightweight techniques that allow debugging at the source level for programs that have been transformed by a trace-based binary dynamic optimizer. Our techniques provide full transparency and hide from the user the effect of dynamic optimizations on code statements and data values. We describe and evaluate an implementation of DeDoc and its techniques that interface a dynamic optimizer with a native debugger. Our experimental results indicate that DeDoc is able to report over 96% of values, that are otherwise not reportable due to code transformations, and incurs less than 1% performance overhead. Naveen Kumar 0002, Bruce R. Childers, Mary Lou Soffa |
CGO | 1 |
| 2007 | Virtual Execution Environments: Support and ToolsabstractIn today's dynamic computing environments, the available resources and even underlying computation engine can change during the execution of a program. Additionally, current trends in software development favor the flexibility and cost-effectiveness of dynamically loaded components and libraries. Because of these trends, there has been increased research interest in virtual execution environments (VEEs) for delivering adaptable software suitable for today's rapidly changing, heterogeneous computing environments. In this project, we have been investigating tools and techniques to support implementation of VEEs using software dynamic translation (SDT). This paper highlights some of our recent results. One significant result is that we have developed novel translation techniques that reduce the memory and runtime overhead of SDT to negligible levels. We have also developed innovative debugging and instrumentation tools for SDT-based software environments. Together, these results make SDT-based systems viable for solving a wide range of pressing problems. The paper concludes with a discussion of how SDT may offer a solution to one such problem-inherent process variation in emerging chip multiprocessors. Apala Guha, Jason Hiser, Naveen Kumar 0002, Jing Yang 0003, Min Zhao 0009, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Kim M. Hazelwood, Mary Lou Soffa |
IPDPS | 3 |
| 2006 | Techniques and tools for dynamic optimizationabstractTraditional code optimizers have produced significant performance improvements over the past forty years. While promising avenues of research still exist, traditional static and profiling techniques have reached the point of diminishing returns. The main problem is that these approaches have only a limited view of the program and have difficulty taking advantage of the actual run-time behavior of a program. We are addressing this problem through the development of a dynamic optimization system suited for aggressive optimization - using the full power of the most beneficial optimizations. We have designed our optimizer to operate using a software dynamic translation (SDT) execution system. Difficult challenges in this research include reducing SDT overhead and determining what optimizations to apply and where in the code to apply them. Another challenge is having the necessary tools to ensure the reliability of software that is dynamically optimized. In this paper, we describe our efforts in reducing overhead in SDT and efficient techniques for instrumenting the application code. We also describe our approach to determine what and where an optimization should be applied. We discuss other fundamental issues in developing a dynamic optimizer and finally present a basic debugger for SDT systems Jason Hiser, Naveen Kumar 0002, Min Zhao 0009, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Mary Lou Soffa |
IPDPS | 2 |
| 2005 | Low overhead program monitoring and profilingabstractProgram instrumentation, inserted either before or during execution, is rapidly becoming a necessary component of many systems. Instrumentation is commonly used to collect information for many diverse analysis applications, such as detecting program invariants, dynamic slicing and alias analysis, software security checking, and computer architecture modeling. Because instrumentation typically has a high run-time overhead, techniques are needed to mitigate the overheads. This paper describes "instrumentation optimizations" that reduce the overhead of profiling for program analysis. Our approach applies transformations to the instrumentation code that reduce the (1) number of instrumentation points executed, (2) cost of instrumentation probes, and (3) cost of instrumentation payload, while maintaining the semantics of the original instrumentation. We present the transformations and apply them for program profiling and computer architecture modeling. We evaluate the optimizations and show that the optimizations improve profiling performance by 1.26-2.63x and architecture modeling performance by 2-3.3x. Naveen Kumar 0002, Bruce R. Childers, Mary Lou Soffa |
PASTE | 1 |
| 2004 | Profile Guided Management of Code Partitions for Embedded SystemsabstractResearchers have proposed to divide embedded applications into code partitions and to download partitions on demand from a wireless code server to enable a diverse set of applications for very tightly constrained embedded systems. This paper describes a new approach for managing the request and storage of code partitions and we explore the benefits of our scheme. Shukang Zhou, Bruce R. Childers, Naveen Kumar 0002 |
DATE | 3 |
| 2003 | Retargetable and Reconfigurable Software Dynamic TranslationabstractSoftware dynamic translation (SDT) is a technology that permits the modification of an executing program's instructions. In recent years, SDT has received increased attention, from both industry and academia, as a feasible and effective approach to solving a variety of significant problems. Despite this increased attention, the task of initiating a new project in software dynamic translation remains a difficult one. To address this concern, and in particular, to promote the adoption of SDT technology into an even wider range of applications, we have implemented Strata, a cross-platform infrastructure for building software dynamic translators. This paper describes Strata's architecture, our experience retargeting it to three different processors, and our use of Strata to build two novel SDT systems - one for safe execution of untrusted binaries and one for fast prototyping of architectural simulators. Kevin Scott, Naveen Kumar 0002, S. Velusamy, Bruce R. Childers, Jack W. Davidson, Mary Lou Soffa |
CGO | 2 |