Recent mobile processors are required to exhibit both low-energy consumption and high performance. To satisfy these requirements, dynamic voltage scaling (DVS) is currently employed. However, its effectiveness will be limited in the future because of shrinking the variable supply voltage range. As an alternative, we previously proposed pipeline stage unification (PSU), which unifies multiple pipeline stages without reducing the supply voltage at a power-saving mode. This paper compares effectiveness of PSU to DVS in current and future process generations. Our evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years.

It has become an important requirement to achieve high performance and low-power consumption at the same time. The dynamic leakage cut-off (DLC) scheme, which controls transistors' threshold voltage by the line on demand, is a technique that potentially satisfies that requirement for a cache. Yet, conventional DLC causes access time to significantly lengthen, and consequently processor performance is unacceptably degraded. This paper proposes a mechanism that suppresses the performance degradation by preactivating cache lines using address prediction before access requests. Our evaluation results show significant performance improvements are achieved with little increase of power consumption.

Latency associated with memory accesses and process communications are one of the most difficult obstacles in constructing a practical massively parallel system. So far, two approaches to hide latencies have been proposed. They are prefetching and multi-threading. An instruction-level data-driven computer is an ideal test-bed for evaluating these latency hiding methods because prefetching and multi-threading are naturally implemented in an instruction-level data-driven computer as unfolding and concurrent execution of multiple contexts. This paper evaluates latency hiding methods on SIGMA-1, a dataflow supercomputer developed in Electrotechnical Laboratory. As a result of evaluation, these methods are effective to hide static latencies but not effective to hide dynamic latencies. Also, concurrent execution of multiple contexts is more effective than prefetching.

The authors propose a priority control scheme for packet switching multistage networks, called priority forwarding, which prevents priority inversion, a situation in which higher priority packets are blocked by lower priority packets. In an N*N omega network, the worst case delay of the priority forwarding scheme on the highest priority packet is O(log/sup 2/ N), while that for round-robin arbitration is O(N). Simulation results show that the priority forwarding scheme offers shorter delays for higher priority packets without throughput degradation and fits least-laxity-first control. The hardware implementation cost of this scheme is relatively small and requires no extra signal lines between routers. Consequently, this scheme offered predictability, scalability, and implementation eligibility.>

In the past, various computer languages aimed at users of dataflow computers have been designed and implemented.VAL, Id and SISAL are famous examples.One concept that is common to such languages is to maintain a sense of functionality by introducing a single assignment rule for all variables.DFCII, Dataflow C II, the language proposed here, is designed for writing practical application programs and system programs that must be executed in parallel on the SIGMA-1.It is the most important dataflow research

This paper describes the research activity on dataflow computing in Japan focusing on dataflow computer development at the Electrotechnical Laboratory (ETL). First, the history of dataflow computer development in Japan is outlined. Some distinguished milestones in the history are mentioned in detail. Second, two types of dataflow computing systems developed at ETL, SIGMA-1 and EM-4, are described with their research goals. The fundamental characteristics of the both systems are given and some comparisons are made. Finally, future problems toward new generation computer systems to meet the challenge of Tera FLOPS machines are discussed.

Structure-flow processing is proposed as a novel scheme for handling data structures such as vectors in data-flow architecture. The main objective of structure-flow processing is to enhance the vector processing performance. In this scheme, the arrival of a data structure unrolls the control structure that processes the data structure itself. A high-level structure is an implementation mechanism of a structure-flow scheme on a practical data-flow computer. Since all the computation is executed by instruction-level data-flow architecture, scalar-level parallelism and function-level parallelism are also fully utilized by this scheme. The SIGMA-1 architecture that supports high-level structure processing is discussed. Performance measurements show that vector programs can be executed three to four times faster than by unfolding using scalar dataflow processing.>

A processing element and a structure element of data flow computer SIGMA-1 for scientific computations is now operational. The elements are evaluated for several benchmark programs. For efficient execution of loop constructs, the sticky token mechanism which holds loop invariants is evaluated and exhibits a remarkable effect. From the standpoint that performance of a single processor of a data flow computer must be comparable to that of a Von Neumann computer, comparison of both computers is discussed and improvement of the SIGMA-1 instruction set is proposed.

Two parallel hashing algorithms based on open and chained hashing are discussed. The parallel chained hashing algorithm is efficient even in the environment where deletion and insertion frequently occur. The chained hashing memory with fewer memory banks has a performance equivalent to that of the open hashing memory.