This paper describes the implementation of a fast neural net simulator on a novel parallel distributed-memory computer. A 60-processor system, named MUSIC (multiprocessor system with intelligent communication), is operational and runs the backpropagation algorithm at a speed of 330 million connection updates per second (continuous weight update) using 32-b floating-point precision. This is equal to 1.4 Gflops sustained performance. The complete system with 3.8 Gflops peak performance consumes less than 800 W of electrical power and fits into a 19-in rack. While reaching the speed of modern supercomputers, MUSIC still can be used as a personal desktop computer at a researcher's own disposal. In neural net simulation, this gives a computing performance to a single user which was unthinkable before. The system's real-time interfaces make it especially useful for embedded applications.

An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models.>

This paper describes a parallel distributed computer architecture called MUSIC (multi signal processor system with intelligent communication). A single processor element (PE) consists of a DSP 96002 from Motorola (60 MFlops), program and data memory and a fast, independent communication interface; all communication interfaces are connected through a communication ring. A system with 30 processor elements (PEs) is operational. It has a peak performance of 1.8 GFlops, an electrical power consumption of about 350 watt (including forced air cooling). It fits into a 19 inch rack. The hardware price of this system is 40000 US $ which means a selling price of approximately 200000 US $. Beside the wellknown Mandelbrot algorithm (601 MFlops sustained), two real applications are at the moment successfully implemented on the system: the backpropagation algorithm for neural net learning results in a peak performance of 150 MCUPS (million connection updates per second) which equals 900 MFlops sustained and the molecular dynamics simulation program MD-Atom (443 MFlops sustained). Other applications of the system are in digital signal processing and finite element computation.>

The authors discuss the MUSIC (multi-signal-processor system with intelligent communication) system, a parallel distributed memory architecture based on digital signal processors (DSPs). A system with 60 processor elements is operational. It has a peak performance of 3.8 GFlops and an electrical power consumption of less than 800 W (including forced air cooling), and it fits into a 19" rack. Two applications (the backpropagation algorithm for neural network learning and molecular dynamics simulations) run about six times faster than on a CRAY Y-MP and two times faster than on a NEC SX-3. A sustained performance of more than 1 GFlops is reached.>

A neurocomputer based on a high-density analog integrated circuit developed in a 3 mum CMOS technology has been built. The 1.6 mmx2.4 mm chip contains 18 neurons and 161 synapses in three layers, and provides 16 inputs and 4 outputs. The weights are stored on storage capacitors of the synapses. A formalization of the error back-propagation algorithm which allows the use of very small nonlinear synapses is shown. The influence of offset voltages in the synapses on the circuit performance is analyzed. Some experimental results are reported and discussed.

The treatment of symmetrical lossless three-conductor transmission lines with arbitrary terminations and umped coupling elements is reduced to a set of four delay elements and analog interface networks modeling the mode conversion in unsymmetrical terminations or coupling elements between the lines. The model can easily be programmed in circuit simulators like SPICE using the respective transmission line models in combination with the above-mentioned interface networks. Crosstalk between bus lines is discussed as an example.>

A parallel computer architecture for real-time image processing is described. The architecture centers on the direct mapping of a static dataflow graph into hardware: each node (or group of nodes) is replaced by a processing element. The processing elements are connected by a flexible and fast communication network based on multiple interruptible buses. A prototype of the system has been built. Many low-level image processing algorithms run in real time at video rate. Applications of the system include real-time computer vision, real-time image enhancement, robotics, and autonomous systems. A color classification algorithm for autonomous vehicle guidance runs at video rate (50 frames/s). For this application, more than 200 million instructions (VAX equivalent) are executed.>

A reconfigurable systolic array is described. The concept centers on the direct mapping of a static data flow into hardware; each node (or group of nodes) of the data flow graph is replaced by a processing element (PE). Several PEs can be grouped together forming an optimal interconnection structure to process subgraphs. This architecture permits implementation of most algorithms that can be described using static data flow graphs. This class of algorithms encompasses most common signal processing applications.>