The error-rate floor phenomenon associated with iterative LDPC decoders has delayed the use of LDPC codes in certain communication and storage systems. Error floors are known to generally be caused by so-called trapping sets which have the effect of confounding the decoder. In this paper, we introduce two techniques that lower the error-rate floors for LDPC-coded partial response (PR) channels which are applicable to magnetic and optical storage. The techniques involve, via external measures, "pinning" one of the bits in each problematic trapping set and then letting the iterative decoder proceed to correct the rest of the bits. We also extend our earlier work on generalized-LDPC (G-LDPC) decoders for error-floor mitigation on the AWGN channel to partial response channels. Our simulations on PR1 and EPR4 channels demonstrate that the floor for the code chosen for this study, a 0.78(2048,1600) quasicyclic LDPC code, is lowered by orders of magnitude, beyond the reach of simulations. Because simulation in the floor region is so time-consuming, a method for accelerating such simulations is essential for research in this area. In this paper, we present an extension of Richardson's importance sampling technique for estimating the level of error floors.

One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC code's Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than floors of the the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.

We examine the performance of a rate-0.9 structured irregular repeat-accumulate (S-IRA) code on a perpendicular magnetic recording (PMR) channel with media noise. To account for the presence of data-dependent media noise, a pattern-dependent-noise-predictive (PDNP) channel detector is employed, in which the prediction filters are trained using the LMS algorithm. We compare the error rate performance of the S-IRA code with that of a Reed-Solomon (RS) code of the same length and rate, with the PDNP detector present in both cases. Our results show that the S-IRA code achieves a gain of over 1 dB relative to the RS code for sector error rates down past 10-4, but only if the columns of its H-matrix are properly permuted. We have also estimated that the linear density gain attainable by the S-IRA code relative to the RS code is about 8% for the operating point we have chosen.

In this paper, we propose a dual-mode decoding technique for product codes in which the rows and columns may comprise either Reed-Solomon (RS) codewords or LDPC codewords. The first decoding mode uses standard hard-decision decoding algorithms on the rows and columns, after which a maximum-likelihood (ML) packet-erasure decoding algorithm is employed for the column code in a second decoding mode. For the second mode, the column code takes on a different character in which "slices" of the row code are treated as packets which are symbols in the column code. The ML decoder for this packet-level column code resolves the erroneous packets (erasures) flagged by the row code or a packet-level CRC code during the first decoding mode. By exploring an application to tape storage, we demonstrate that this dual-mode decoding method can dramatically improve the performance of a product code. Moreover, the complexity added by the second mode is manageable.