An incremental algorithm for computation of sums of squares is presented that is suitable for both most-significant-bit- (MSB-)first and least-significant-bit- (LSB-)first bit-sequential operation. By exploiting symmetry properties of numerical values and evaluation times in the bit-product matrix, it is shown how incremental multipliers can be converted to perform squaring at reduced hardware cost, and sum of squaring at a hardware cost to that of scalar multiplication. By the elimination of redundant computation, existing hardware modules are either reduced in size or assigned to the evaluation of a second squaring computation. The corresponding hardware architectures are derived from a simple conversion of existing incremental scalar multipliers. This conversion process is less practical on standard serial/parallel or serial-pipeline multipliers. A digit-on-line algorithm is outlined for magnitude extraction operations on plane vectors.>

With reference to the above mentioned paper (see ibid., vol.C-35, p.896-901 (1986)), it is stated that the authors' introduction, in which they claim that the references all deal with algorithms for processing unsigned operands, is erroneous. One of their references most certainly does not deal with unsigned operands, as a two's complement number system is one of the module interfacing conventions germane to R. Lyon's (1981) methodology. Moreover, in the authors' conclusions they state that they 'have now extended bit-sequential multiplication to signed, two's complement binary operands', which may give the (doubtless unintended) impression that this has not been done before.>

Digital hardware may be used to generate waveforms as well as to process already-existing waveforms. Several digital synthesis techniques are in use today, most of whose advantages lie in their computational efficiency rather than their utility. Only the methods of synthesis known as additive and subtractive, however, are accompanied by a suitable analysis technique, allowing the accurate extraction of parameters from real waveforms for subsequent use in synthesis. With the advent of VLSI, these techniques are becoming economically attractive for analysis and synthesis of sound. An approach to musical signal processing, based on additive synthesis, is presented.

A structure is proposed for adaptive removal of echoes from communications signals. It consists of an FIR adaptive filter which models the echoing channel, and an IIR programmable filter which performs the echo removal. This technique allows the use of a recursive filter without incurring the stability problems normally associated with adaptive fIR filters. The adaptive filter programs the weights of the recursive filter via a simple transform, which may in fact be incorporated in the adaptive process. Results of computer simulations are presented, showing convergence on PRBS sequences corrupted by echoing channels.