During the last years, a new type of systems-on-chip called, reconfigurable systems-on-chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, the authors present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of system's functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains

Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods.

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are essen tial for the design of such a complex system. It is sho wn how a C++ programming approach outperforms traditional HDL-based methods.

This paper presents a new approach to module generation. It is based on the observation that a function, realized by a module instance (e.g. a 16-bit multiplier) when restricted to a sub-function, can be realized by a reduction of the instance to a sub-instance (e.g. a 8-bit multiplier). This reduction is performed automatically by REDUSA. It offers important advantages in both the construction and verification aspects of module generators.

This paper presents a new approach to module generation. It is based on the observation that a function, realized by a module instance (e.g. a 16-bit multiplier) when restricted to a sub-function, can be realized by a reduction of the instance to a sub-instance (e.g. a 8-bit multiplier). This reduction is performed automatically by REDUSA. It offers important advantages in both the construction and verification aspects of module generators.