In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C+AB/sup 2/ in finite fields GF(2/sup m/). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2/sup m/). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.

This paper presents two new systolic arrays to realize Euclid's algorithm for computing inverses and divisions in finite fields GF(2/sup m/) with the standard basis representation. One of these two schemes is parallel-in parallel-out, and the other is serial-in serial-out. The former employs O(m/sup 2/) area complexity to provide the maximum throughput in the sense of producing one result every clock cycle, while the latter achieves a throughput of one result per m clock cycles using O(m log,m) area complexity. Both of the proposed architectures are highly regular and, thus, well suited to VLSI implementation. As compared to existing related systolic architectures with the same throughput performance, the proposed parallel-in parallel-out scheme reduces the hardware complexity (and, thus, the area-time product) by a factor of O(m) and the proposed serial-in serial-out scheme by a factor of O(m/log/sub 2/m).