The study of bridging faults (or short circuits that occur between conducting paths) has become increasingly important with the advent of LSI technology. To date, only a very few papers have been published on this topic. Specifically, little is known regarding undetectable bridging faults. More importantly, what has yet to be explored are the effects of undetectable bridging faults on the tests designed to detect stuck-at faults.

A switching theoretic framework for the study of interconnection networks is developed. An equivalence relationship between networks is defined. Single-stage and multistage networks that are particularly useful for single-instruction multiple-data stream (SIMD) machines are studied. It is shown that the networks form two distinct equivalence classes under this definition of equivalence relationship. It is shown that any multistage network can be easily modified to realize the permutations that are admissible by any other network which is equivalent to it.

An algebraic generalization of the well-known binary q-function array to a multivalued q-function array is presented. It is possible to associate tree-structure realizations for binary q-functions and multivalued q-functions. Synthesis of multivalued functions using this array is very simple.

Fan-out-free networks of AND, OR, NOT, EXOR, and MAJORITY gates are considered. Boolean functions for which such networks exist are defined to be fan-out free. The paper solves the following problems regarding the fan-out-free networks and functions.

A nonexhaustive procedure for obtaining minimal Reed-Muller canonical (RMC) forms of switching functions is presented. This procedure is a modification of a procedure presented earlier in the literature and enables derivation of an upper bound on the number of RMC forms to be derived to choose a minimal one. It is shown that the task of obtaining minimal RMC forms is simplified in the case of symmetric functions and self-dual functions.

The problem of fault detection and location in tree networks of two input EXCLUSIVE-OR (EOR) gates is considered. The fault model assumes that an EOR gate can change to any other function of its two inputs except the equivalence function. An efficient procedure for single fault location is presented. In the worst case the number of tests necessary to locate single faults is bounded by a linear function of the number of input variables. Constructive upper bounds are obtained for the number of tests to detect multiple faults. Optimality of these bounds is argued and extension of results to other types of networks is considered.

Canonical forms for m-valued functions referred to as m-Reed–Muller canonical (m-RMC) forms that are a generalization of RMC forms of two-valued functions are proposed. m-RMC forms are based on the operations ⊕m (addition mod m) and .m (multiplication mod m) and do not, as in the cases of the generalizations proposed in the literature, require an m-valued function for m not a power of a prime, to be expressed by a canonical form for M-valued functions, where M > m is a power of a prime. Methods of obtaining the m-RMC forms from the truth vector or the sum of products representation of an m-valued function are discussed. Using a generalization of the Boolean difference to m-valued logic, series expansions for m-valued functions are derived.

It is shown that at most, n + 3 tests are required to detect any single stuck-at fault in an AND gate or a single faulty EXCLUSIVE OR (EOR) gate in a Reed-Muller canonical form realization of a switching function.