Fault injection attacks are a growing concern for the security of cyber systems. To mitigate these threats, hardware protections are often complemented by a series of software countermeasures, the implementation of which can be complex, time-consuming, and error-prone even for cybersecurity experts. In this article, we introduce SecSwift, a compiler-based framework dedicated to the generation of these software countermeasures. SecSwift offers a carefully balanced architecture that augments the usual code generation flow of the LLVM compiler at selected points in the front-end, middle-end and back-end. In its current state, SecSwift leverages classical control-flow integrity and data-flow protections, generalized to their xs.A simulation-based instruction-set-level fault injection test campaign validates the proposed approach and demonstrates the robustness of the generated countermeasures. This campaign notably features a comparison between SecSwift and nZDC, which is widely considered a benchmark for countermeasure code generation. Experimental results indicate that SecSwift is on a par with, and often better than, nZDC in terms of fault detection and code size.Finally, we show that SecSwift can easily generate countermeasures for 32-bit RISC-V RV32E processors, which have only 16 general-purpose registers. Clearly, SecSwift’s high-level approach is a distinct advantage for architectures with small register files—an area where low-level approaches based on partitioning between main and shadow registers struggle.

Modern compiler implementations use the Static Single Assignment representation [5] as a way to efficiently implement optimizing algorithms. However this representation is not well adapted to architectures with a predicated instruction set. The ψ-SSA representation was first introduced in [11] as an extension to the Static Single Assignment representation. The ψ-SSA representation extends the SSA representation such that standard SSA algorithms can be easily adapted to an architecture with a fully predicated instruction set. A new pseudo operation, the ψ operation, is introduced to merge several conditional definitions into a unique definition.

Static Single Assignment form is an intermediate representation that uses /spl Phi/ instructions to merge values at each confluent point of the control flow graph. /spl Phi/ instructions are not machine instructions and must be renamed back to move instructions when translating out of SSA form. Without a coalescing algorithm, the out of SSA translation generates many move instructions. Leung and George [A. L. Leung et al., (1999)] use a SSA form for programs represented as native machine instructions, including the use of machine dedicated registers. For this purpose, they handle renaming constraints thanks to a pinning mechanism. Pinning /spl Phi/ arguments and their corresponding definition to a common resource is also a very attractive technique for coalescing variables. Extending this idea, we propose a method to reduce the /spl Phi/-related copies during the out of SSA translation, thanks to a pinning-based coalescing algorithm that is aware of renaming constraints. We implemented our algorithm in the STMicroelectronics Linear Assembly Optimizer [B. Dupont de Dinechin et al., (2000)]. Our experiments show interesting results when comparing to the existing approaches of Leung and George [A. L. Leung et al., (1999)], Sreedhar et al. [V. Sreedhar et al., (1999)], and Appel and George for register coalescing [L. George et al., (1996)].

We present a framework that allows translation of predicated code into the static single assignment (SSA) form, and simplifies application of the SSA-based optimizations to predicated code. In particular we represent predicate join points in the program by the /spl Psi/-functions similar to the /spl Phi/-functions of the basic SSA. The SSA-based optimizations (such as constant propagation) can be applied to predicated code by simply specifying additional rules for processing the /spl Psi/-functions. We present efficient algorithms for constructing, and then for removing the /spl Psi/-functions at the end of SSA processing. Our algorithm for translating out of the /spl Psi/-SSA splits predicated live ranges into smaller live ranges active under disjoint predicates. The experimental evaluation on a set of predicated benchmarks demonstrates efficiency of our approach.

The ST120 Digital Signal Processor -Micro-Controller Unit (DSP{MCU) core was designed by STMicroelectronics in order to meet the ever-increasing digital signal processing requirements of portable and consumer applications.Like other recent high-end DSP{MCU cores, the ST120 blends traditional DSP features with modern Instruction-Level Parallelism (ILP) capabilities.Compiler management o f the ST120 features presents a unique challenge to the code generation.The ST120 Linear Assembly Optimizer (LAO) eectively exploits instructionlevel parallelism, while enabling compact code size.In this paper, we focus on the LAO implementation of the SSA representation, the IF-conversion, the SLIW scheduling, and the LAO i m p r o vements to register allocation.This includes solutions to problems that arise when compiler optimizations are applied to assembly-level, already predicated code.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific