This paper presents silicon results for two such proposed fault models: the cell aware fault model and the small delay defect fault model. The corresponding tests including cell-aware ATPG tests and Fast-than at-speed TDF tests are evaluated on an industrial design. Results from a high volume manufacturing experiment on a 65nm Serial Attached SCSI (SAS) RAID-On-a-Chip (ROC) device are presented. The incremental value of these fault models and tests beyond our current test flow is discussed.

Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.

Clock gating is widely used in modern integrated circuits as a means of reducing dynamic power consumption. In this paper we present a comprehensive analysis of the impact of clock gating during test. We then propose a new type of test point called Clock Gate Test Points. Similar to classic test point techniques, clock gate test points help in increasing the test coverage as well as reducing the number of test patterns and thus test time. We also outline techniques for applying the proposed test points in a design. We present the results of coverage improvement and test pattern reduction with the proposed method for several large industrial circuits. Our results show that with the proposed method, in many cases, more than 2.0% improvement in transition delay fault coverage can be achieved and the number of test patterns can be reduced by more than 50% for the same fault coverage. Furthermore, the proposed test points add very little area overhead and do not impact the circuit performance.

The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work to show that such tests can also be used for testing additional transistor stuck-open faults. Experimental results for coverage improvement in several ISCAS-89 benchmark circuits will be discussed.

Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects by any given pattern set. We demonstrate that the proposed metric overcomes the identified shortcomings of previously published approaches. For several ISCAS and industrial circuits, we generate test patterns and compare their SDD coverage values using different methods. Experimental results also demonstrate that the proposed method is several times faster to compute. Finally, we evaluate different testing strategies for screening small delay defects.

We present a new test data compression technique that achieves 10times to 40times compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach

We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented

We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.

Testing of delay faults require two pattern tests. Broadside and skewed-load testing are two approaches to test for delay faults in scan designs. The broadside approach is often preferred over the skewed-load approach in designs that also use the system clock for scan operations, since skewed-load requires a fast (at-speed) scan enable signal while broadside testing does not. In this paper, we propose new scan flip-flops to improve delay fault coverage for circuits with scan using broadside tests. The proposed flip-flops do not require a control signal to switch at-speed. This is a distinct advantage as the design effort required for timing closure of such control signals is significant. We also propose a circuit topology based flip-flop selection procedure that offers a scalable method for increasing the transition fault coverage. Experimental results on industrial circuits are included

We present a complete system for failure analysis of full-scan circuits. A novel scheme has been proposed to handle multiple faults up to a certain extent by ranking the faults according to the likelihood of being present in the defective part. The user can interactively recompute the suspect fault list by changing some parameters. If the suspect fault list is large, we generate new test patterns to distinguish the faults in the suspect list. User can iterate over a defective part several times until the suspect fault list is reasonably small. Then each suspect site is probed using E-beam. This tool is integrated into design environment of LSI Logic Corporation and produced good results when applied on a few industry circuits.