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M. Cemil Azizoglu

dblp:78/5294 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 67% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip
routing algorithms
0.012000
Lower Bounds on Communication Loads with Optimal Placements in Torus Networks · IEEE Trans. Computers 2000
Electronic design automation › physical design › routing › message routing
shortest-path routing
0.012000
Lower Bounds on Communication Loads with Optimal Placements in Torus Networks · IEEE Trans. Computers 2000
Interconnection networks and networks-on-chip › network topology
torus network
0.012000
Lower Bounds on Communication Loads with Optimal Placements in Torus Networks · IEEE Trans. Computers 2000

Methods — techniques the papers use, named apart from their topics

combinatorial lower bound analysis · 0.0
YearPublicationVenuePosition
2004 The bisection width and the isoperimetric number of arrays
M. Cemil Azizoglu, Ömer Eeciolu
Discret. Appl. Math.1
2000 Lower Bounds on Communication Loads with Optimal Placements in Torus Networks
abstract
Fully populated torus-connected networks, where every node has a processor attached, do not scale well since load on edges increases superlinearly with network size under heavy communication, resulting in a degradation in network throughput. In a partially populated network, processors occupy a subset of available nodes and a routing algorithm is specified among the processors placed. Analogous to multistage networks, it is desirable to have the total number of messages being routed through a particular edge in toroidal networks increase at most linearly with the size of the placement. To this end, we consider placements of processors which are described by a given placement algorithm parameterized by k and d: We show formally, that to achieve linear communication load in a d-dimensional k-torus, the number of processors in the placement must be equal to ck/sup d-1/ for some constant c. Our approach also gives a tighter lower bound than existing bounds for the maximum load of a placement for arbitrary number of dimensions for placements with sufficient symmetries. Based on these results, we give optimal placements and corresponding routing algorithms achieving linear communication load in tori with arbitrary number of dimensions.
M. Cemil Azizoglu, Ömer Egecioglu
IEEE Trans. Computers1