Structured ASICs have recently emerged as a mid-way between cell-based ASICs with high NRE costs and FPGAs with high unit costs. Though the structured ASIC fabric attacks mask and other fixed cost it does not solve verification, particularly physical verification issues with ASICs or logic errors missed by simulation which would require re-spins. These can be avoided by testing in-system with an FPGA and migrating the FPGA design to a closely coupled structured ASIC fabric. Here we describe a practical methodology for a fast, push-button, and thorough verification approach tying an FPGA prototype to a matching structured-ASIC implementation for cost-reduction. Our focus is the equivalence verification between the respective revisions of a design, including netlist, compiler settings, macro-block parameters, timing constraints, pin layout and resource count.

This paper describes a new procedure for generating very large realistic benchmark circuits which are especially suited for the performance evaluation of field programmable gate array partitioning algorithms. These benchmark circuits can be generated quickly. The generation of a netlist of 100 K configurable logic blocks (500 K equivalent gates), for instance, takes only 2 min on a standard UNIX workstation. The analysis of a large number of netlists from real designs lead us to identify the following five different kinds of subblocks: regular combinational logic, irregular combinational logic, combinational and sequential logic, memory blocks, and interconnections. Therefore, our generator integrates a subgenerator for each of these types of netlist. The comparison of the partitioning results of industrial netlists with those obtained from generated netlists of the same size shows that the generated netlists behave similarly to the originals in terms of average filling rate and average pin utilization.

This paper describes a new procedure for generating very large realistic benchmark circuits which are especially suited for the performance evaluation of FPGA partitioning algorithms.These benchmark circuits can be generated quickly.The generation of a netlist of 1OOK CLBs (500K equivalent gates), for instance, takes only two minutes on a standard UNIX workstation.The analysis of a large number of netlists from real designs lead us to identify the following five different kinds of sub-blocks: Regular combinational logic, irregular combinational logic, combinational and sequential logic, memory blocks, and interconnections.Therefore, our generator integrates a sub-generator for each of these types of netlist.The comparison of the partitioning results of industrial netlists with those obtained from generated netlists of the same size shows that the generated netlists behave similarly to the originals in terms of average filling rate and average pin utilization.