Smart Robots are an integral part of the 4th Industrial Revolution. Its integration as essential components in robot-based services is not straightforward. Each robot is a cyber-physical system (CPS) where a mechanical part operates under the control of a digital board(s). Modeling and simulation of such devices has specificities to be taken into account. Model-Driven Design (MDD) has proven to be a powerful System Engineering methodology able to cope with the complexity of services built as a system of CPSs (CPSoS). In this paper, a methodology is proposed to seamlessly integrate robots into a MDD framework so that the whole service can be simulated and its performance, analyzed. Although the methodology is valid for robots in general, it has been assessed on a drone-based service.

The idea of having drones into the national airspace raises serious concerns. These concerns are for nearly all spectrum of society which ranges from government facilities and aviation authorities to private citizens. To guarantee a high level of safety and security, drones must be implemented as highly constrained systems with a certain number of functions (technologies). In this paper, we identify the key technologies for drones based on their common and specific usages. These technologies are grouped into four categories: U-space capabilities, system functions, payloads, and tools. We also list the contributions of COMP4DRONES project in terms of improving technologies and easing drone customization including its safe operations.

The purpose of this paper is to introduce run time monitoring infrastructures and to analyze trace data inside a well-established component-based methodology. The goal is to show the concept among different monitoring requirements by defining a general reference architecture that can be adapted to different scenarios. Starting from design artifacts, generated by a system engineering modeling tool, and source code automatically generated from UML models, a custom Hardware monitoring sub-system infrastructure will be presented. This sub-system will be able to generate run-time artifacts for run-time verification. We will show how the framework provides round-trip support in the development chain, injecting monitoring requirements from design models down to code and its execution on the platform and trace data back to the models, where the expected behavior will then be compared with the actual behavior. This approach will be used towards optimizing design models for specific properties (e.g, for system performance), using a specific constraint approach compliant with UML standards. Industrial and custom use cases will be used to demonstrate the effectiveness of this approach in real scenarios.

Efficient design of complex multiprocessor embedded systems requires fast technologies for early system cosimulation and evaluation. Host-compiled simulation has been proposed as an option for this purpose, since it enables accurately timed modeling at high simulation speeds. To achieve high accuracy, simulation technology has to consider internal details of the processing system, such as the modeling of processor pipelines or the estimation of cache misses. However, the modeling of these details must involve low overhead to ensure simulation speed. This paper proposes adding the modeling of the impact of a write buffer in write-through policies. The scheme presented is oriented to maximizing the accuracy vs. speed balance, proposing a static solution that results in no additional simulation overhead.

The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.

This paper presents how to integrate formally based models relying on the Synchronous Dataflow Model-of- Computation (MoC) in a UML/MARTE component-based application model. This model corresponds to a flexible and expressive modelling methodology, which facilitates finding and building an application model with the intended semantics, but does not help to ensure a strict fulfilment of functional and extrafunctional requirements. However, this capability has become a need in the context of modelling mixed-criticality applications. This paper shows how the component-based UML/MARTE models captured in such a flexible methodology can integrate parts transformable into synchronous data-flows. This formalism facilitates the analysis of the functional and extra-functional properties of such parts. Specifically, the paper shows a set of modelling patterns which can be translated into SDF counterparts. Relying on these patterns, a framework has been implemented which enables a bi-directional interoperability between the UML/MARTE models abiding the patterns and the formally-based ForSyDe methodology.

short-paper Share on A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems Authors: F. Herrera Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, Spain Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, SpainView Profile , P. Peñil Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, Spain Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, SpainView Profile , E. Villar Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, Spain Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, SpainView Profile Authors Info & Claims SCOPES '15: Proceedings of the 18th International Workshop on Software and Compilers for Embedded SystemsJune 2015Pages 88–91https://doi.org/10.1145/2764967.2784777Published:01 June 2015Publication History 9citation113DownloadsMetricsTotal Citations9Total Downloads113Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The increasing complexity in the development of embedded system applications is necessitating system modularization, parallelization and component portability. Finding the best solution to combine component reuse and platform optimization is not an easy and straightforward task, especially when considering the different APIs supported to provide communication and concurrency on the different boards. Thus, in order to reduce designer effort, the development of automatic synthesis tools operating from high level models is emerging. In this context, this paper presents a methodology for automating system deployment on different platforms supporting distinct APIs. The process starts from a high-level description based on UML/MARTE and provides automatic code generation for interconnection and deployment of system components. This automatic process enables exploration of different possibilities both in the component allocation and in the resulting concurrency, requiring only minimal designer effort. Different APIs such as POSIX, OpenMP, OpenStream, TCP-IP and MCAPI are covered to provide the required flexibility for platform support and reuse.

The increase in complexity of electronic systems has opened the way to the use of different types of operating systems working together. The development of these systems requires simulation infrastructures where the entire system, including all its OSs, can be simulated, both for functional verification and performance evaluation. However, the generation of such simulation infrastructures with current technologies usually requires a huge effort that high-level engineers cannot support. In order to solve this problem, the paper presents a solution for simulating systems composed of different kinds of OSs. The approach is based on native simulation and presents an example combining Linux and Win32 systems in a single simulation. This example ensures usability since these are two of the most complex OSs commonly integrated in electronic devices. Nevertheless, the idea can also be extended to support other OSs. As a result, engineers can take advantage of an infrastructure capable of modeling complex architectures with different operating systems requiring relatively little design effort, for early system evaluation at the beginning of the design process.

In this article, we present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to assist the designer in the development of parallel embedded systems, from executable specifications to target-specific implementation and debugging on a multicore platform. This tool chain will offer and implement several parallelization strategies, reflecting the functional and non-functional constraints of the system, and driving the designer into incremental parallelization and adaptation steps. The second objective of the project is to develop monitoring and control techniques in the middleware of the system capable to automatically adapt platform services to application requirements and therefore reduce power consumption transparently.

The consideration of an embedded device's power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today's heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties that enables fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow is currently under implementation in the COMPLEX FP7 European integrated project.

This paper presents a framework which, starting from a UML/MARTE model of the embedded system, relies on an enhanced IP-XACT description of the platform for the automatic generation of fast performance executable models. The IP-XACT description of the HW architecture is automatically generated from the UML/MARTE model. The enhancement proposed extends the current capabilities of the IP-XACT standard in order to add semantic information to the HW architecture and to support the integration of Hardware Dependent Software (HdS). This way, HW and SW aspects of the integration of a component in a virtual platform model are covered. The applicability of the proposed extensions is shown by supporting the proposed IP-XACT descriptions at the front-end of a simulation infrastructure suited for fast performance assessment, and for supporting design space exploration.

Efficient design of large multiprocessor embedded systems requires fast, early performance modeling techniques. Native co-simulation has been proposed as a fast solution for evaluating systems in early design steps. Annotated SW execution can be performed in conjunction with a virtual model of the HW platform to generate a complete system simulation. To obtain sufficiently accurate performance estimations, the effect of all the system components, as processor caches, must be considered. ISS-based cache models slow down the simulation speed, greatly reducing the efficiency of native-based co-simulations. To solve the problem, cache modeling techniques for fast native co-simulation have been proposed, but only considering instruction-caches. In this paper, a fast technique for data-cache modeling is presented, together with the instrumentation required for its application in native execution. The model allows the designer to obtain cache hit/miss rate estimations with a speed-up of two orders of magnitude with respect to ISS. Miss rate estimation error remains below 5% for representative examples.

Approximate timed co-simulation has been proposed as a fast solution for system modeling in early design steps. This co-simulation technique enables the simulation of systems at speeds close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, enabling efficient design space exploration and system refinement. To achieve fast simulation speeds, first the SW code is pre-annotated with time information and then it is natively executed, performing what is called native-based co-simulation. To obtain sufficiently accurate performance estimations, the effect of the system components must be considered. Among them, processor caches are really important, as they have a strong impact on the overall system performance. However, no efficient techniques for cache modeling in native-based co-simulation have been proposed. Previous works considering caches apply slow cache models based on tag search, similar to ISS-based models. This solution slows down the simulation speed, greatly reducing the efficiency of native based co-simulations. In this paper, a high-level instruction cache model is proposed, along with the required instrumentation for native simulation. This model allows the designer to obtain cache hit/miss rate estimations with simulation speeds very close to native execution. Results present a speed-up of two orders of magnitude with respect to ISS and one order of magnitude regarding previous approaches in native simulation. Miss rate estimation error remains below 5%.

Nowadays, complexity of embedded systems is increasing. This increasing complexity is due to the behavioural heterogeneity and the variety in the nature of system components. Additionally, it is essential to deal with the massive concurrency of such components. Therefore, as a consequence of these critical system aspects, the modelling of current embedded systems has become a challenge for the designers. In order to address this challenge, the UML/MARTE profile has been created. The MARTE profile provides the essential capabilities to develop design methodologies able to cover most of the main design steps. However, to understand and later to model current complex embedded systems in a univocal, well-defined way, formal foundations are required. This paper introduces a formal framework able to support methodologies that tackle the design of current embedded systems using the MARTE profile. In this paper the Generic Resource Modelling (GRM) subprofile of MARTE is used. The required formal foundations are provided by the Formal System Design (ForSyDe) formalism. This paper defines an abstraction methodology able to generate the corresponding ForSyDe model from the MARTE concurrency resources.

AADL has been proposed for designing and analyzing SW and HW architectures for real-time mission-critical embedded systems. However, it does not support the expression of the behavior of a system in detail, so a behavioral annex has been defined. In this paper we propose AADS+, an AADL simulation tool that supports the performance analysis of the AADL specification, enriched with behavior specifications, throughout the refinement process from the initial system architecture until the complete, detailed application and execution platform are developed. In this way, AADS+ enables the verification of the initial timing constraints during the complete design process.

The increase of computational power in embedded systems has allowed integrating together hard real-time tasks and rich applications. Complex SW infrastructures containing both RTOS and GPOS are required to handle this complexity. To optimally map system functionality to the hard-RT SW domain, to the general purpose SW domain or to HW peripherals, early performance evaluations at the first steps of the design process are required. Approximate timed co-simulation has been proposed as a fast solution for system modeling at early design steps. This co-simulation technique allows simulating systems at speed close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, allowing efficient design space exploration and system refinement. To achieve fast simulation speed, the SW code is pre-annotated with time information. The annotated code is then natively executed, performing what is called native-based co-simulation. Previous native-based simulation environments are not prepared to model multi-OS systems, so the performance evaluation of the different SW domains is not possible. This paper proposes a new embedded system modeling solution considering dual RTOS/GPOS systems. A real Linux-based infrastructure has been modeled an integrated into a state-of-the-art co-simulation environment. The resulting solution is capable of modeling and evaluating all HW and SW system components providing the designer with valuable information for early system optimization and design space exploration.

Due to the increasing complexity of embedded systems, new design methodologies have to be adopted, since traditional techniques are no longer efficient. Model-based engineering enables the designer to confront these concerns using the architecture description of the system as the main axis during the design cycle. Defining the architecture of the system before its implementation enables the analysis of constraints imposed on the system from the beginning of the design cycle until the final implementation. AADL has been proposed for designing and analyzing SW and HW architectures for real-time mission-critical embedded systems. Although the Behavioral Annex improves its simulation semantics, AADL is a language for analyzing architectures and not for simulating them. In this paper, AADS, an AADL simulation tool is presented. AADS supports the performance analysis of the AADL specification throughout the refinement process from the initial system architecture until the complete, detailed application and execution platform are developed. In this way, AADS enables the verification of the initial timing constraints during the complete design process.

Provides an abstract of the tutorial presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings.

This paper proposes a SystemC-based specification methodology of adaptive embedded systems to be implemented on a platform including one or more processors, thus supporting the execution of embedded software, and digital hardware with capabilities of partial dynamic reconfiguration (DRHW). For it, it proposes the collaboration of two specification methodologies: HetSC and OSSS+R. The main issues for the integration of these specification methodologies are addressed. This includes how to install and use them together, which is the structure of the specification, how adaptivity is specified for SW and DRHW implementation, and the syntactical and semanticual issues related to the MoC interface implicit in their connection.

Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology tools for automatic hardware and software synthesis for adaptive architectures.

This work proposes a methodology which enables heterogeneous specification of complex, electronic systems in SystemC supporting the integration of components under different models of computation (MoCs). This feature is necessary in order to deal with the growing complexity, concurrency, and heterogeneity of electronic embedded systems. The specification methodology is based on the SystemC standard language. Nevertheless, the use of SystemC for heterogeneous system specification is not straightforward. The first problem to be addressed is the efficient and predictable mapping of untimed events required by abstract MoCs over the discrete-event MoC on which the SystemC simulation kernel is based. This mapping is essential in order to understand the simulation results provided by the SystemC model of those MoCs. The specification methodology proposes the set of rules and guidelines required by each specific MoC. Moreover, the methodology supports a smooth integration of several MoCs in the same system specification. A set of facilities is provided covering the deficiencies of the language. These facilities constitute the methodology-specific library called HetSC. The methodology and associated library have been demonstrated to be useful for the specification of complex, heterogeneous embedded systems supporting essential design tasks such as performance analysis and SW generation.

Early estimation of the execution time of real-time embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires taking into account the impact of the underlying RTOS. As a consequence, RTOS modeling is becoming an active research area. SystemC provides a framework for multiprocessing, HW/SW co-simulation at several abstraction levels. In this paper, a SystemC library for POSIX modeling and simulation is presented. By using the library, the SystemC specification using POSIX functions is converted automatically into a timed simulation estimating the execution time of the application SW running on the POSIX platform. The library works directly on the source code. Therefore, it provides an early and fast estimation of the performance of the system as a consequence of the architectural mapping decisions. Although accuracy is lower than when using lower-level techniques, it supports high-level design-space exploration as simulation time is significantly less than RT (ISS) simulation.

This paper presents a heterogeneous specification methodology built on top of the standard SystemC kernel. The methodology enables abstract specification supporting heterogeneity, which in this context entails the ability to describe and connect parts of the system specification under different models of computation (MoCs). A main and distinguishing contribution of the methodology is that the support is provided while maintaining the standard kernel of SystemC unchanged, by means of a set of specification rules and a heterogeneous support library built on top of the SystemC standard library. This is possible thanks to an abstraction technique that can integrate any new MoC that can be abstracted over the underlying discrete-event simulation kernel. Primitives, guidelines and rules of the specification methodology, including those related to heterogeneous support, and the basis of the abstraction technique are described. Experimental results demonstrate the benefits of the methodology.

As both the ITRS and the Medea+ DA Roadmaps have highlighted, early performance estimation is an essential step in any SoC design methodology based on International Technology Roadmap for Semiconductors (2001) and The MEDEA+ Design Automation Roadmap (2002). This paper presents a C++ library for timing estimation at system level. The library is based on a general and systematic methodology that takes as input the original SystemC source code without any modification and provides the estimation parameters by simply including the library within a usual simulation. As a consequence, the same models of computation used during system design are preserved and all simulation conditions are maintained. The method exploits the advantages of dynamic analysis, that is, easy management of unpredictable data-dependent conditions and computational efficiency compared with other alternatives (ISS or RT simulation, without the need for SW generation and compilation and HW synthesis). Results obtained on several examples show the accuracy of the method. In addition to the fundamental parameters needed for system-level design exploration, the proposed methodology allows the designer to include capture points at any place in the code. The user can process the corresponding captured events for unrestricted timing constraint verification.

In this chapter we show the ability to specify with SystemC under the restrictions imposed by several model of computations, namely CSP, KPN and SR. Specifying under these MoCs provides some important properties, specially determinism and more protection against blocking, which are also important when implementation process is faced. In most cases, standard primitive SystemC channels or a combined use of them is suitable for specifying under these MoC restrictions. Nevertheless we provide some new specific and compatible channels providing important features, as dynamic checking of restrictions or atomic use. These channels represent an extension of the standard SystemC library.

No abstract available.

No abstract available.