EDBT 2026 Demo / reviewers in the wild / expert
Chusei Ogawa
dblp:78/5828
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
layout compaction |
0.0 | 1 | 1993 | A Compaction Method for Full Chip VLSI Layouts · DAC 1993 |
Electronic design automation
physical design |
0.0 | 1 | 1993 | A Compaction Method for Full Chip VLSI Layouts · DAC 1993 |
Methods — techniques the papers use, named apart from their topics
parallel processing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | A Compaction Method for Full Chip VLSI LayoutsabstractAn algorithm independent layout compaction method for full chip layouts is proposed.The partitioning compaction method cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout.A 16-bit CPU core (28.8Ktransistors) layout was compacted on a standard workstation using this method.Both the computer memory usage and processing time were reduced.Parallel processing is pcssible to further speed up the computation. Joseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori |
DAC | 4 |