Among other deep learning (DL) architectures, the convolutional neural network (CNN) has wide applications in speech recognition, face detection, natural language processing, and computer vision. Multiply and Accumulate (MAC) unit is a core part of CNN and requires large computations and memory resources. They result in more power dissipation for low-power embedded devices. Hence, the hardware implementation of CNN to produce high throughput is one of the challenges nowadays. Therefore, sparsity is introduced in weights by a non-linear method with a minor compromise in accuracy. Experimental results also show the enhancement of 52% sparsity with a 4% loss in accuracy. In addition, an indexing module is proposed to perform Single Instruction Multiple Data (SIMD) operations in the fully connected layer to perform only effective operations without multiplication. This module is used along with sparsity to offer better results as compared to SOTA methods. Cadence RTL compiler results show that the proposed indexing module saves 1.3 nJ of energy as compared to the existing methods.

In the semiconductor landscape, safeguarding integrated circuits against Hardware Trojans (HT) is critical.To address this pressing concern, supervised machine learning (ML) has emerged as a promising defense mechanism for HT detection. However, the vulnerability of supervised ML-based defense mechanisms to adversarial attacks poses a substantial challenge, potentially compromising model prediction performance. This paper presents a label flipping poisoning attack, strategically targeting supervised ML-based HT detection systems during the pre-silicon IC design phase. Leveraging the power of the Isolation Forest, our method first identifies potential Trojan nets through a process of random partitioning, flips their labels, and perturbs the model training process. Further, random subsampling is applied to select a subset of Trojan-free samples, whose labels are also flipped. This model-independent, untargeted, and black-box attack is evaluated against Trust-Hub & DeTrust Benchmarks, resulting in a substantial reduction in model recall, challenging the reliability of ML-based HT detection systems.

Edge-enabled Deep Learning (DL) solutions for Predictive Quality Inspection (PQI) of products in Industry 4.0 are mostly designed for static manufacturing environments. In general, modern manufacturing processes are dynamic in nature. In this context, continual learning-based model retraining accommodates the dynamism for PQI of multiple processes (tasks) using a single DL model. However, the impact of the task ordering in sequentially arriving tasks and solution to reduce this impact on the overall PQI is yet to be solved. To this end, a novel mechanism using a light-weight similarity analysis module is introduced in the quality prediction system at the resource-limited edge. Sequential training of tasks above a similarity threshold (γ) is preferred, and dissimilar tasks are overlooked to train a separate model. This enables a PQI system to hover over training efficiency and model sustainability. The experimental results validate the impact of task order and the effectiveness of the proposed similarity-based analysis to reduce this impact by 70% on the model's overall performance in the real-world use case of plastic bricks.

Approximate computing is an emerging computing technique for designing energy- and resource-efficient arithmetic circuits for error-resilient applications. Square root (SQR) computation is a fundamental and complex operation in various signal/image processing tasks. It demands high resource and energy consumption, making the square-rooter a crucial design element. This brief proposes a low-complexity logarithmic-based energy-efficient approximate square rooter (LESQ) for computing integer SQR using simple addition and shift operations. A partial error compensation scheme is also suggested for improved accuracy. The proposed approximate square rooter also enables various accuracy configurable modes to tradeoff error with hardware efficiency for targeted application requirements. LESQ achieves energy- and area-delay savings of up to 80% and 60%, respectively, compared to an accurate array-based square-rooter design. The proposed approximate design is tested on error-tolerant applications, such as image processing and amplitude modulation (AM) communication system.

The present paper embodies a technique for on-the-fly remote reconfiguration of mobile device for power optimization according to the requested quality of service (RQoS) from user. The method is initiated by mobile device user who sends RQoS parameters to remote server, where the multimedia algorithms are re-optimized as per RQoS, and a new bit-stream is transmitted to reconfigure the device for low power with acceptable degradation in quality. Experimental results show that the approach is able to reduce bitwidth by 64.31% to 73.95% for varying PSNR from 40dB to 26dB. Much higher power savings can be achieved if user is willing to tolerate more quality degradation.

The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded into an environment supporting array processor design for real world applications. Another aspect of the tool is the intended support of advanced fault tolerance techniques in an early design phase. More emphasis is given to fabrication-time/run-time fault tolerance techniques and to find a cost-effective solution with the evaluation of optimality criteria and real design tradeoff.>